A2F200M3F-1FGG484 Actel, A2F200M3F-1FGG484 Datasheet - Page 17

• Manufacturer Part Number: A2F200M3F-1FGG484
• Description: FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
• Manufacturer: Actel

Specifications of A2F200M3F-1FGG484

• Processor Series: A2F200
• Core: ARM Cortex M3
• Number Of Logic Blocks: 8
• Maximum Operating Frequency: 120 MHz
• Number Of Programmable I/os: 161
• Data Ram Size: 4608 bit
• Delay Time: 200 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 1 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 200000
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VCCxxxxIOBx Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
VCC Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
VCC and VCCxxxxIOBx ramp-up trip points are about 100 mV higher than ramp-down trip points. This
specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the
following:
PLL Behavior at Brownout Condition
The Microsemi SoC Products Group recommends using monotonic power supplies or voltage regulators
to ensure proper power-up behavior. Power ramp-up should be monotonic at least until VCC and
VCCPLLx exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case
(see
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25
V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down
Behavior of Low Power Flash Devices" chapter of the
information on clock and lock recovery.
Internal Power-Up Activation Sequence
Output buffers, after 200 ns delay from input buffer activation
3. Chip is in the SoC Mode.
•
•
1. Core
2. Input buffers
Figure 2-1 on page 2-6
During programming, I/Os become tristated and weakly pulled up to VCCxxxxIOBx.
JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O
behavior.
for more details).
R e v i s i o n 6
SmartFusion Intelligent Mixed Signal FPGAs
ProASIC3 FPGA Fabric User’s Guide
2 -5
for