LCMXO256C-3TN100C Lattice, LCMXO256C-3TN100C Datasheet - Page 2
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LCMXO256C-3TN100C
Manufacturer Part Number
LCMXO256C-3TN100C
Description
CPLD - Complex Programmable Logic Devices 256 LUTS 78 I/O
Manufacturer
Lattice
Series
MachXOr
Datasheet
1.LCMXO640C-3TN100C.pdf
(95 pages)
Specifications of LCMXO256C-3TN100C
Memory Type
SRAM
Number Of Macrocells
128
Delay Time
4.9 ns
Number Of Programmable I/os
78
Operating Supply Voltage
1.8 V, 2.5 V, 3.3 V
Supply Current
13 mA
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-100
Mounting Style
SMD/SMT
Supply Voltage (max)
3.465 V
Supply Voltage (min)
1.71 V
Cpld Type
FLASH
No. Of Macrocells
256
No. Of I/o's
78
Propagation Delay
4.9ns
Global Clock Setup Time
1.8ns
Frequency
420MHz
Supply Voltage Range
1.71V To 3.465V
Rohs Compliant
Yes
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
4.9ns
Voltage Supply - Internal
1.71 V ~ 3.465 V
Number Of Logic Elements/blocks
-
Number Of Gates
-
Number Of I /o
78
Operating Temperature
0°C ~ 85°C
Mounting Type
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LCMXO256C-3TN100C
Manufacturer:
LATTICE
Quantity:
5 600
Company:
Part Number:
LCMXO256C-3TN100C
Manufacturer:
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Company:
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Company:
Part Number:
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Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LCMXO256C-3TN100C
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LATTICE
Quantity:
20 000
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© 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
April 2006
Features
■ Non-volatile, Infinitely Reconfigurable
■ Sleep Mode
■ TransFR™ Reconfiguration (TFR)
■ High I/O to Logic Density
■ Embedded and Distributed Memory
Table 1-1. MachXO Family Selection Guide
LUTs
Dist. RAM (Kbits)
EBR SRAM (Kbits)
Number of EBR SRAM Blocks (9 Kbits)
V
Number of PLLs
Max. I/O
Packages
100-pin TQFP (14x14 mm)
144-pin TQFP (20x20 mm)
100-ball csBGA (8x8 mm)
132-ball csBGA (8x8 mm)
256-ball ftBGA/fpBGA (17x17 mm)
324-ball ftBGA (19x19 mm)
1. fpBGA package
CC
Voltage
• Instant-on – powers up in microseconds
• Single chip, no external configuration memory
• Excellent design security, no bit stream to
• Reconfigure SRAM based logic in milliseconds
• SRAM and non-volatile memory programmable
• Supports background programming of
• Allows up to 100x static current reduction
• In-field logic update while system operates
• 256 to 2280 LUT4s
• 73 to 271 I/Os with extensive package options
• Density migration supported
• Lead free/RoHS compliant packaging
• Up to 27.6 Kbits sysMEM™ Embedded Block
• Up to 7.5 Kbits distributed RAM
• Dedicated FIFO control logic
required
intercept
through JTAG port
non-volatile memory
RAM
Device
1.2/1.8/2.5/3.3V
LCMXO256
256
2.0
78
78
78
0
0
0
1-1
MachXO Family Data Sheet
■ Flexible I/O Buffer
■ sysCLOCK™ PLLs
■ System Level Support
Introduction
The MachXO is optimized to meet the requirements of
applications traditionally addressed by CPLDs and low
capacity FPGAs: glue logic, bus bridging, bus interfac-
ing, power-up control, and control logic. These devices
bring together the best features of CPLD and FPGA
devices on a single chip.
1.2/1.8/2.5/3.3V
• Programmable sysIO™ buffer supports wide
• Up to two analog PLLs per device
• Clock multiply, divide, and phase shifting
• IEEE Standard 1149.1 Boundary Scan
• Onboard oscillator
• Devices operate with 3.3V, 2.5V, 1.8V or 1.2V
• IEEE 1532 compliant in-system programming
LCMXO640
range of interfaces:
power supply
159
− LVCMOS 3.3/2.5/1.8/1.5/1.2
− LVTTL
− PCI
− LVDS, Bus-LVDS, LVPECL, RSDS
640
159
113
101
6.0
74
74
0
0
0
1
1.2/1.8/2.5/3.3V
LCMXO1200
1200
6.25
211
113
101
211
9.2
73
1
1
Introduction
1.2/1.8/2.5/3.3V
Introduction_01.2
LCMXO2280
2280
27.6
271
113
101
211
271
Data Sheet
7.5
73
3
2