LCMXO256C-3TN100C Lattice, LCMXO256C-3TN100C Datasheet - Page 16
![CPLD - Complex Programmable Logic Devices 256 LUTS 78 I/O](/photos/16/2/160258/tqfp-100_sml.jpg)
LCMXO256C-3TN100C
Manufacturer Part Number
LCMXO256C-3TN100C
Description
CPLD - Complex Programmable Logic Devices 256 LUTS 78 I/O
Manufacturer
Lattice
Series
MachXOr
Datasheet
1.LCMXO640C-3TN100C.pdf
(95 pages)
Specifications of LCMXO256C-3TN100C
Memory Type
SRAM
Number Of Macrocells
128
Delay Time
4.9 ns
Number Of Programmable I/os
78
Operating Supply Voltage
1.8 V, 2.5 V, 3.3 V
Supply Current
13 mA
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-100
Mounting Style
SMD/SMT
Supply Voltage (max)
3.465 V
Supply Voltage (min)
1.71 V
Cpld Type
FLASH
No. Of Macrocells
256
No. Of I/o's
78
Propagation Delay
4.9ns
Global Clock Setup Time
1.8ns
Frequency
420MHz
Supply Voltage Range
1.71V To 3.465V
Rohs Compliant
Yes
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
4.9ns
Voltage Supply - Internal
1.71 V ~ 3.465 V
Number Of Logic Elements/blocks
-
Number Of Gates
-
Number Of I /o
78
Operating Temperature
0°C ~ 85°C
Mounting Type
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
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Price
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Part Number:
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Quantity:
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Company:
Part Number:
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Quantity:
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Part Number:
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20 000
Lattice Semiconductor
Figure 2-13. Memory Core Reset
For further information on the sysMEM EBR block, see the details of additional technical documentation at the end
of this data sheet.
EBR Asynchronous Reset
EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the
reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-14. The GSR input to the
EBR is always asynchronous.
Figure 2-14. EBR Asynchronous Reset (Including GSR) Timing Diagram
If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after
the EBR read and write clock inputs are in a steady state condition for a minimum of 1/f
release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.
These instructions apply to all EBR RAM, ROM and FIFO implementations. For the EBR FIFO mode, the GSR sig-
nal is always enabled and the WE and RE signals act like the clock enable signals in Figure 2-14. The reset timing
rules apply to the RPReset input vs the RE input and the RST input vs. the WE and RE inputs. Both RST and
RPReset are always asynchronous EBR inputs.
These instructions apply to all EBR RAM, ROM and FIFO implementations.
Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled
GSRN
RSTA
RSTB
Programmable Disable
Reset
Clock
Clock
Enable
Memory Core
2-13
Output Data
L
L
D
D
Latches
CLR
CLR
SET
SET
Q
Q
MachXO Family Data Sheet
Port A[17:0]
Port B[17:0]
MAX
(EBR clock). The reset
Architecture