S29GL256P11TFI010 Spansion Inc., S29GL256P11TFI010 Datasheet - Page 46

• Manufacturer Part Number: S29GL256P11TFI010
• Description: Flash 3V 256Mb Mirrorbit highest address110ns
• Manufacturer: Spansion Inc.

Specifications of S29GL256P11TFI010

• Memory Type: NOR
• Memory Size: 256 Mbit
• Access Time: 110 ns
• Data Bus Width: 8 bit, 16 bit
• Architecture: Uniform
• Interface Type: Page-mode
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Current: 50 mA
• Mounting Style: SMD/SMT
• Operating Temperature: + 85 C
• Package / Case: TSOP-56
• Memory Configuration: 128K X 16
• Ic Interface Type: Parallel
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: TSOP
• No. Of Pins: 56
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

9. Power Conservation Modes
9.1
9.2
9.3
9.4
44
8.6.3
8.6.4
Standby Mode
Automatic Sleep Mode
Hardware RESET# Input Operation
Output Disable (OE#)
Write Pulse “Glitch Protection”
Power-Up Write Inhibit
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
If WE# = CE# = RESET# = V
rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
When the system is not reading or writing to the device, it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,
independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET#
inputs are both held at V
is ready to read data. If the device is deselected during erasure or programming, the device draws active
current until the operation is completed. I
specification
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for t
CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the system. I
represents the automatic sleep mode current specification.
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET#
is driven low for at least a period of t
all outputs, and ignores all read/write commands for the duration of the RESET# pulse. The device also
resets the internal state machine to reading array data. The operation that was interrupted should be
reinitiated once the device is ready to accept another command sequence to ensure data integrity.
When RESET# is held at V
not within V
RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
When the OE# input is at V
impedance state.
SS
± 0.3 V, the standby current is greater.
D a t a
CC
SS
IH
± 0.3 V. The device requires standard access time (t
IL
, output from the device is disabled. The outputs are placed in the high
S29GL-P MirrorBit
± 0.3 V, the device draws I
and OE# = V
S h e e t
RP
, the device immediately terminates any operation in progress, tristates
CC4
IH
in “DC Characteristics” represents the standby current
ACC
( A d v a n c e
during power up, the device does not accept commands on the
TM
Flash Family
+ 30 ns. The automatic sleep mode is independent of the
CC
reset current (I
I n f o r m a t i o n )
CC5
). If RESET# is held at V
CE
S29GL-P_00_A3 November 21, 2006
) for read access, before it
CC6
in
Section 11.6
IL
but