XR16L580IL-F Exar Corporation, XR16L580IL-F Datasheet - Page 4

• Manufacturer Part Number: XR16L580IL-F
• Description: UART Interface IC UART
• Manufacturer: Exar Corporation

Specifications of XR16L580IL-F

• Data Rate: 1 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: QFN
• No. Of Channels: 1
• Uart Features: Selectable RX And TX FIFO Trigger Levels, Automatic Software Flow Control, Complete Modem Interface
• Supply Voltage Range: 2.25V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XR16L580
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
PIN DESCRIPTIONS
Pin Descriptions
DATA BUS INTERFACE
MODEM OR SERIAL I/O INTERFACE
(R/W#)
(IRQ#)
N
IOW#
IOR#
(NC)
CS#
INT
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
TX
AME
QFN
P
24-
14
15
16
24
23
22
21
20
13
17
11
IN
4
3
2
7
6
#
QFN
P
28-
16
17
18
28
27
26
25
24
13
11
19
IN
4
3
2
7
6
#
QFN
P
32-
17
18
19
32
31
30
29
14
12
20
IN
5
4
3
1
8
7
#
TQFP
PIN#
48-
26
27
28
47
46
45
44
43
19
16
30
11
4
3
2
8
T
(OD)
I/O
YPE
O
O
I
I
I
I
Address data lines [2:0]. These 3 address lines select one of the
internal registers in UART channel A/B during a data bus transac-
tion.
Data bus lines [7:0] (bidirectional).
When 16/68# pin is at logic 1, the Intel bus interface is selected and
this input becomes read strobe (active low). The falling edge insti-
gates an internal read cycle and retrieves the data byte from an
internal register pointed by the address lines [A2:A0], puts the data
byte on the data bus to allow the host processor to read it on the ris-
ing edge.
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input is not used.
When 16/68# pin is at logic 1, it selects Intel bus interface and this
input becomes write strobe (active low). The falling edge instigates
the internal write cycle and the rising edge transfers the data byte
on the data bus to an internal register pointed by the address lines.
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input becomes read (logic 1) and write (logic 0) signal.
This input is chip select (active low) to enable the device.
When 16/68# pin is at logic 1 for Intel bus interface, this output
become the active high device interrupt output. The output state is
defined by the user through the software setting of MCR[3]. INT is
set to the active mode when MCR[3] is set to a logic 1. INT is set to
the three state mode when MCR[3] is set to a logic 0. See MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, this output
becomes the active low device interrupt output (open drain). An
external pull-up resistor is required for proper operation.
UART Transmit Data or infrared encoder data. Standard transmit
and receive interface is enabled when MCR[6] = 0. In this mode, the
TX signal will be a logic 1 during reset or idle (no data). Infrared
IrDA transmit and receive interface is enabled when MCR[6] = 1. In
the Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is a logic 0. If it is not used, leave it
unconnected.
4
D
ESCRIPTION
REV. 1.4.1