XR16L580IL-F Exar Corporation, XR16L580IL-F Datasheet - Page 29

UART Interface IC UART

XR16L580IL-F

Manufacturer Part Number
XR16L580IL-F
Description
UART Interface IC UART
Manufacturer
Exar Corporation
Datasheet

Specifications of XR16L580IL-F

Data Rate
1 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.25 V
Supply Current
3 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Package / Case
QFN
No. Of Channels
1
Uart Features
Selectable RX And TX FIFO Trigger Levels, Automatic Software Flow Control, Complete Modem Interface
Supply Voltage Range
2.25V To 5.5V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XR16L580IL-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
Company:
Part Number:
XR16L580IL-F
Quantity:
15 000
Company:
Part Number:
XR16L580IL-F
Quantity:
15 000
Company:
Part Number:
XR16L580IL-F
Quantity:
15 000
Company:
Part Number:
XR16L580IL-F
Quantity:
15 000
Part Number:
XR16L580IL-FN
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
REV. 1.4.1
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
Logic 0 = No parity.
Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
LCR BIT-5 = logic 0, parity is not forced (default).
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
Table 9
LCR B
X
0
0
1
1
IT
for parity selection summary below.
-5 LCR B
SMALLEST 2.25V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE
BIT-2
0
1
1
X
0
1
0
1
IT
-4 LCR B
T
ABLE
LENGTH
5,6,7,8
W
6,7,8
0
1
1
1
1
ORD
5
9: P
IT
-3
ARITY SELECTION
29
Forced parity to space, “0”
Force parity to mark, “1”
S
TOP BIT LENGTH
(B
P
1 (default)
ARITY SELECTION
IT TIME
1-1/2
Even parity
Odd parity
No parity
2
(
S
))
XR16L580

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