5171N32-U THAT Corporation, 5171N32-U Datasheet - Page 11

• Manufacturer Part Number: 5171N32-U
• Description: Microphone Preamplifiers High-Perform Digital Pre-Amp Controller
• Manufacturer: THAT Corporation

Specifications of 5171N32-U

• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 17 V
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current: 8.3 mA
• Supply Voltage (max): 17 V
• Supply Voltage (min): 3 V
• Thd Plus Noise: 0.0003 %
• Available Set Gain: 13.6 dB to 68.6 dB
• Input Offset Voltage: +/- 1.5 mV
• Maximum Operating Temperature: + 85 C
• Package / Case: QFN-32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

THAT5171 High-Performance
Digital Preamplifier Controller IC
(C
pins 20 (D
the digital output driver bus. Pins 12 (D
13 (V
respectively, through short, low-inductance paths.
directly under the 5171. Note that the part includes
back-to-back diodes limiting the maximum voltage
difference between these nodes. If even on a transient
basis (e.g., supply spikes) a voltage difference of over
0.5 V exists between A
will flow which may damage the part.
integrated differential servo is required for proper
operation of the system as shown in the application
schematics. By using the servo amplifier in feedback,
output offset can be controlled over a wide range of
gains.
ommends that C
the size of C
contributing noise to the preamplifier, we recom-
mend that the servo’s output be divided down by
approximately 1000:1 by the combination of R
and R
Zero Crossing Detector
enabled or disabled. (See the digital control section
below for details.) When enabled, it prevents gain
changes from occurring until the differential output
signal waveform is within ±5mV of zero. It is possible
that in unusual cases where significant low-frequency
material is present, the zero-crossing detector may
unacceptably delay a gain change from taking place.
A timeout, set by R
gain change to occur within R
requested, even if zero crossing is enabled.
Digital Control
Reset (RST pin)
isters to their default state (see register definitions in
SPI Port section for default values after reset). This
pin is typically connected to system reset or to a port
on the host microcontroller.
16
CS
SCLK
DIN
DOUT
THAT recommends one decoupling capacitor
A
As described above (in the Theory section), the
In order to optimize settling behavior, THAT rec-
The integrated zero-crossing detector may be
Asserting the RST pin low forces all internal reg-
) for the digital power supply, placed close to
GND
DD
8
Signal
/R
) should be connected to pins 20 and 21,
2
and D
.
GND
4
) and 21 (V
and C
GND
12
and C
5
16
17
18
19
T
. As well, to avoid the servo from
Pin
should be connected together
and C
GND
Tel: [phone]; Fax: [phone]; Web: www.thatcorp.com
DD
13
THAT Corporation; 45 Sumner Street; Milford, MA 01757-1656; USA
), as these pins connect to
be approximately one-half
and D
T
Input
Input
Input
Output/Tristate
, is provided to force a
T
Copyright © 2010, THAT Corporation; All rights reserved.
C
T
mS of the time it is
I/O
GND
, large currents
GND
) and Pin
Device chip select input, active low. An SPI transfer begins with a high-to-low
CS transition and ends with a low-to-high CS transition. When CS is high,
SCLK transitions are ignored.
SPI serial clock input. An SPI master supplies this clock with frequencies up
to 10MHz. Data is clocked into the DIN pin on the rising edge of SCLK. Data
is clocked out of DOUT pin on the falling edge of SCLK.
SPI serial data input (Master-Out, Slave-In). DIN is MSB first.
SPI serial data output (Master-In, Slave-Out). DOUT is a tristate output.
DOUT is tristated when CS is high. DOUT is MSB first.
Table 3. SPI signals.
7
/R
Page 11 of 20
1
address via the GPO[2:0] pins. These pins are typi-
cally connected to pull-up and pull-down resistors to
establish the chip address, and serve as general pur-
pose outputs during runtime. THAT Corporation
intends to offer features in future versions of the
5171 that will be configured via a pull up resistor on
GPO3. Thus, GPO3 should be pulled low by a resis-
tor of 100 kΩ or less on early designs before these
new features become available.
Busy (BSY pin)
gain setting is not equal to the value in the GAIN reg-
ister, i.e. when a gain update is pending a zero-
crossing. This pin may be monitored by the host
microcontroller (e.g. connected to an external inter-
rupt pin) in order to hold off a new gain command
until the previous gain command has been executed.
goes low when a pending gain change has been made.
If finer gain steps are implemented in subsequent
processing (typically via DSP) this signal can be used
to assist in synchronizing subsequent gain changes
with those implemented by the 5171. Note, of course,
that latency in A/D conversion must be considered
when attempting to synchronize digital with analog
gain updates.
Gain Update Modes (and TRC pin)
selected by the MODE bits in the Control/Status Reg-
ister (Table 13), as follows.
1) IMMEDIATE Mode: Gain updates are made
2) ZERO-CROSSING Mode: Updates are made on
During reset, the 5171 reads the 3-bit SPI
The BSY pin is asserted high when the current
Note that in ZERO-CROSSING mode, the BSY pin
The 5171 supports two gain update modes,
immediately following a rising edge on the /CS
pin.
the next output signal zero-crossing after a rising
edge on the /CS pin. An RC time constant con-
nected to the TRC pin (R
establishes a time-out period in case a zero-
crossing does not occur within a desired time
window. The zero-crossing time-out function
operates as follows:
A) C
beginning of an SPI command sequence), and is
allowed to start charging when /CS goes high
(the end of an SPI command sequence).
T
is discharged when /CS goes low (the
Function
Document 600133 Rev 04
T
/C
T
in Figures 3~6)