WM8983GEFL/V Wolfson Microelectronics, WM8983GEFL/V Datasheet - Page 85

• Manufacturer Part Number: WM8983GEFL/V
• Description: Audio CODECs Mbl Multimedia CODEC w/ 1W Speaker Driver
• Manufacturer: Wolfson Microelectronics

Specifications of WM8983GEFL/V

• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-32
• Minimum Operating Temperature: - 25 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Production Data
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Table 56 Clock Control
The CKLSEL bit selects the internal source of the Master clock from the PLL (CLKSEL=1) or from
MCLK (CLKSEL=0). When the internal clock is switched from one source to another using the
CLKSEL bit, the clock originally selected must generate at least one falling edge after the CLKSEL
has changed for the switching of clocks to be successful. For example the sequence for switching
between the PLL and MCLK should be;
R6
Clock
Generation
Control
REGISTER
ADDRESS
1.
2.
3.
Change CLKSEL 1 -> 0
Wait for at least one falling edge from PLL generated clock
Disable the PLL (PLLEN=0)
0
4:2
7:5
8
BIT
MS
BCLKDIV
MCLKDIV
CLKSEL
LABEL
0
000
010
1
DEFAULT
Sets the chip to be master over LRC and
BCLK
0=BCLK and LRC clock are inputs
(Slave mode)
1=BCLK and LRC clock are outputs
generated by the WM8983 (Master
mode)
Configures the BCLK and LRC output
frequency, for use when the chip is in
Master mode.
000=divide by 1 (BCLK=SYSCLK)
001=divide by 2 (BCLK=SYSCLK/2)
010=divide by 4
011=divide by 8
100=divide by 16
101=divide by 32
110=reserved
111=reserved
Sets the division for either the MCLK or
PLL clock output (selected by CLKSEL)
000=divide by 1
001=divide by 1.5
010=divide by 2 (LRC=SYSCLK/256)
011=divide by 3
100=divide by 4
101=divide by 6
110=divide by 8
111=divide by 12
Controls the source of the clock for all
internal operation:
0=MCLK
1=PLL output
DESCRIPTION
PD, Rev 4.3, May 2010
WM8983
85