WM8731SEFL Wolfson Microelectronics, WM8731SEFL Datasheet - Page 46

• Manufacturer Part Number: WM8731SEFL
• Description: Audio CODECs Stereo Codec with H/P
• Manufacturer: Wolfson Microelectronics

Specifications of WM8731SEFL

• Number Of Adc Inputs: 1
• Number Of Dac Outputs: 1
• Conversion Rate: 96 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, I2S)
• Operating Supply Voltage: - 0.3 V to + 3.63 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFN EP
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 2 ADC/2 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8731 / WM8731L
w
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
The WM8731/L can be controlled using a 3-wire serial interface. SDIN is used for the program data,
SCLK is used to clock in the program data and CSB is use to latch in the program data. The 3-wire
interface protocol is shown in Figure 33.
Figure 33 3-Wire Serial Interface
Notes:
1.
2.
3.
2-WIRE SERIAL CONTROL MODE
The WM8731/L supports a 2-wire MPU serial interface. The device operates as a slave device only.
The WM8731/L has one of two slave addresses that are selected by setting the state of pin 15,
(CSB).
Figure 34 2-Wire Serial Interface
Notes:
1.
2.
Table 25 2-Wire MPU Interface Address Selection
To control the WM8731/L on the 2-wire bus the master control device must initiate a data transfer by
establishing a start condition, defined by a high to low transition on SDIN while SCLK remains high.
This indicates that an address and data transfer will follow. All peripherals on the 2-wire bus respond
to the start condition and shift in the next eight bits (7-bit address + R/W bit). The transfer is MSB
first. The 7-bit address consists of a 6-bit base address + a single programmable bit to select one of
two available addresses for this device (see Table 24). If the correct address is received and the
R/W bit is ‘0’, indicating a write, then the WM8731/L will respond by pulling SDIN low on the next
clock pulse (ACK). The WM8731/L is a write only device and will only respond to the R/W bit
indicating a write. If the address is not recognised the device will return to the idle condition and wait
for a new start condition and valid address.
SCLK
SDIN
B[15:9] are Control Address Bits
B[8:0] are Control Data Bits
CSB is edge sensitive not level sensitive. The data is latched on the rising edge of CSB.
B[15:9] are Control Address Bits
B[8:0] are Control Data Bits
SCLK
SDIN
CSB
START
CSB STATE
0
1
B15
R ADDR
B14
B13
B12
R/W
B11
ACK
B10
ADDRESS
0011010
0011011
B9
DATA B15-8
B8
B7
B6
ACK
B5
B4
DATA B7-0
B3
PD, Rev 4.8, April 2009
B2
B1
ACK
Production Data
B0
STOP
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