ARM-JTAG-EW Olimex Ltd., ARM-JTAG-EW Datasheet - Page 8

Programmers & Debuggers HI SPEED ARM USB W/TARGET PWR 2-5V

ARM-JTAG-EW

Manufacturer Part Number
ARM-JTAG-EW
Description
Programmers & Debuggers HI SPEED ARM USB W/TARGET PWR 2-5V
Manufacturer
Olimex Ltd.
Datasheet

Specifications of ARM-JTAG-EW

Positions/sockets
1
Description/function
JTAG Probe
Core Architecture
ARM
Core Sub-architecture
ARM7, Cortex-M0, Cortex-M3
Ic Product Type
Debugger
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
ARM MCUs
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
1701507 25R4408
5. External event breakpoints
5.1.
Overview
ARM-JTAG-EW has the ability to halt the target CPU upon detecting an
external event like a current/voltage spike/drop, external input trigger,
external input pulse detection.
External Breakpoints Block Diagram is given on page 9.
External events can be defined with a simple C-like expression like this
(see page 9 for more information):
So when ARM-JTAG-EW detects that U
will shift a request to the target CPU to halt.
Multiple inputs can be mixed into one event:
WARNING:
corresponding action by ARM-JTAG-EW. Due to the limited sampling rate
of analogue signals, ARM-JTAG-EW cannot detect instantly changes on its
inputs. Also note that shifting the JTAG sequence for requesting a target
CPU halt also takes time, depending on the TCK frequency. Heavy USB
traffic can also influence the response time.
(3000<U_tg && U_tg<3600)
(3000<U_tg && U_tg<3600) || I_tgpwr>200
There is always some time between an actual event and the
TG
>3000mV AND U
TG
<3600mV, it

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