LFXP2-5E-B-EVN Lattice, LFXP2-5E-B-EVN Datasheet - Page 16

MCU, MPU & DSP Development Tools LatticeXP2 Brevia Dev kit

LFXP2-5E-B-EVN

Manufacturer Part Number
LFXP2-5E-B-EVN
Description
MCU, MPU & DSP Development Tools LatticeXP2 Brevia Dev kit
Manufacturer
Lattice
Series
-r
Type
FPGAr

Specifications of LFXP2-5E-B-EVN

Processor To Be Evaluated
LFXP2-5E-6TN144C
Data Bus Width
8 bit
Interface Type
RS-232, JTAG, SPI
Operating Supply Voltage
3.3 V
Silicon Manufacturer
Lattice Semiconductor
Silicon Family Name
LatticeXP2
Kit Contents
Evaluation Board, USB Cables, AC Adapter, Quick Start Guide
Features
Serial RS232 Interface, JTAG Interface
Svhc
No
Rohs Compliant
Yes
Contents
Board, Cables, Documentation, Power Supply
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
LFXP2-5E-6TN144C

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LFXP2-5E-B-EVN
Manufacturer:
Lattice
Quantity:
8
Lattice Semiconductor
SRAM Interface
The LatticeXP2 Brevia Evaluation Board provides 1Mbit of asynchronous SRAM memory in a 128K x 8-bit configu-
ration.
Table 7.
Configuration Interface
Jumper 5 controls the XP2 CFG0 input control pin.
Table 8. Configuration Interface
The factory default setting on J5 is to leave it unshunted. CFG0 has a weak pullup resistor.
SRAM Interface
FPGA SRAM 1 Mbit (U2)
SRAM Signal Name
SRAM_Web
SRAM_CSb
SRAM_Oeb
Addr_10
Addr_11
Addr_12
Addr_13
Addr_14
Addr_15
Addr_16
Data_0
Data_1
Data_2
Data_3
Data_4
Data_5
Data_6
Data_7
Addr_0
Addr_1
Addr_2
Addr_3
Addr_4
Addr_5
Addr_6
Addr_7
Addr_8
Addr_9
CFG0
1
0
16
FPGA Pin
Position
Number
Jumper
119
120
121
122
123
124
125
127
129
130
131
132
133
134
137
138
141
142
143
144
1-2
2-3
10
1
2
5
6
7
8
9
LatticeXP2 Brevia Development Kit
User’s Guide

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