LED7707 STMicroelectronics, LED7707 Datasheet - Page 15

• Manufacturer Part Number: LED7707
• Description: LED Drivers 6-ROW 85mA LED DRIV BOOST REG LCD PANEL
• Manufacturer: STMicroelectronics

Specifications of LED7707

• High Level Output Current: 85 mA
• Operating Supply Voltage: 4.5 V to 36 V
• Maximum Supply Current: 1 mA
• Maximum Power Dissipation: 2.3 W
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Package / Case: VFQFPN-24
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LED7707
Equation 4
In addition, when the FSW pin is tied to AVCC, the LED7707 uses a default 660 kHz fixed
switching frequency, allowing to save a resistor in minimum component-count applications.
Figure 10. Multiple device synchronization
The FSW pin can also be used as synchronization input, allowing the LED7707 to operate
both as master or slave device. If a clock signal with a 220 kHz minimum frequency is
applied to this pin, the device locks synchronized. The signal provided to the FSW pin must
cross the 270 mV threshold in order to be recognized. The minimum pulse width which
allows the synchronizing pulses to be detected is 270 ns. An Internal time-out allows
synchronization as long as the external clock frequency is greater than 220 kHz.
Keeping the FSW pin voltage lower than 270 mV for more than 4.5 µs results in a stop of the
device switching activity. Normal operation is resumed as soon as FSW rises above the
mentioned threshold and the soft-start sequence is repeated.
The SYNC pin is a synchronization output and provides a 35 % (typ.) duty-cycle clock when
the LED7707 is used as master or a replica of the FSW pin when used as slave. It is used to
connect multiple devices in a daisy-chain configuration or to synchronize other switching
converters running in the system with the LED7707 (master operation). When an external
synchronization clock is applied to the FSW pin, the internal oscillator is over-driven: each
switching cycle begins at the rising edge of clock, while the slope compensation (
ramp starts at the falling edge of the same signal. Thus, to prevent sub-harmonic instability
(see
duty-cycle when the boost converter is working in continuous-conduction mode (CCM) in
order to assure that the slope compensation is effective (starts with duty-cycle lower than
40%)
Section 5.1.6
R
FSW
FSW
), the external synchronization clock is required to have a 40 % maximum
AVCC
LED7707
MASTER
SGND
SYNC
R
FSW
=
F
2
SW
5 .
FSW
LED7707
SLAVE
SYNC
Operation description
SGND
SYNC
Figure 11
Sync Out
AM00587v1
15/47
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