WJLXT971ALC.A4-857344 Cortina Systems Inc, WJLXT971ALC.A4-857344 Datasheet - Page 5

• Manufacturer Part Number: WJLXT971ALC.A4-857344
• Description: TXRX ETH 10/100 SGL PORT 64-LQFP
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT971ALC.A4-857344

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1008-1040-2

LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
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Cortina Systems
Block Diagram ............................................................................................................................... 11
64-Ball PBGA: Ball Assignments .................................................................................................. 13
64-Pin LQFP Package: Pins Assignments ................................................................................... 14
Management Interface Read Frame Structure ............................................................................. 28
Management Interface Write Frame Structure ............................................................................. 28
MII Interrupt Logic ......................................................................................................................... 29
Initialization Sequence .................................................................................................................. 31
Hardware Configuration Settings .................................................................................................. 34
Clocking for 10BASE-T ................................................................................................................. 38
Clocking for 100BASE-X .............................................................................................................. 38
Clocking for Link Down Clock Transition ...................................................................................... 39
Loopback Paths ............................................................................................................................ 41
100BASE-X Frame Format ...........................................................................................................42
100BASE-TX Data Path ............................................................................................................... 43
100BASE-TX Reception with No Errors ....................................................................................... 43
100BASE-TX Reception with Invalid Symbol ............................................................................... 44
100BASE-TX Transmission with No Errors .................................................................................. 44
100BASE-TX Transmission with Collision .................................................................................... 44
Protocol Sublayers ....................................................................................................................... 45
LED Pulse Stretching ................................................................................................................... 52
Typical Twisted-Pair Interface - Switch ......................................................................................... 55
Typical Twisted-Pair Interface - NIC ..............................................................................................56
Typical Media Independent Interface ............................................................................................ 57
Typical Interface - LXT971A PHY to 3.3 V Fiber PHY................................................................... 58
Typical Interface LXT971A PHY to 5 V Fiber PHY........................................................................ 59
Typical Interface - LXT971A PHY to Triple PECL-to-PECL Logic Translator............................... 60
100BASE-TX Receive Timing - 4B Mode ...................................................................................... 66
100BASE-TX Transmit Timing - 4B Mode ..................................................................................... 67
100BASE-FX Receive Timing ....................................................................................................... 68
100BASE-FX Transmit Timing ...................................................................................................... 69
10BASE-T Receive Timing ...........................................................................................................70
10BASE-T Receive Timing ............................................................................................................ 70
10BASE-T Transmit Timing .......................................................................................................... 72
10BASE-T Jabber and Unjabber Timing ...................................................................................... 73
10BASE-T SQE (Heartbeat) Timing ............................................................................................. 73
Auto-Negotiation and Fast Link Pulse Timing ............................................................................... 74
Fast Link Pulse Timing .................................................................................................................. 74
MDIO Input Timing ........................................................................................................................ 75
MDIO Output Timing...................................................................................................................... 75
Power-Up Timing ........................................................................................................................... 76
RESET_L Pulse Width and Recovery Timing ............................................................................... 76
PHY Identifier Bit Mapping ...........................................................................................................81
PBGA Package Specification ........................................................................................................ 94
LQFP Package Specifications ....................................................................................................... 95
Link Establishment Overview ...................................................................................................... 35
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
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