SPEAR600-2 STMicroelectronics, SPEAR600-2 Datasheet
SPEAR600-2
Specifications of SPEAR600-2
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SPEAR600-2 Summary of contents
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... Medical lab/diagnostics equipment, wireless access devices, home appliances, residential control and security systems, digital picture frames, and bar-code scanners/readers. Table 1. Device summary Temp. Order code range SPEAR600-2 - °C Doc ID 16259 Rev 2 SPEAr600 Package Packing PBGA420 ( Tray 2.06 mm) 1/95 www.st.com ...
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... System controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.18.1 2.19 Clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.20 Vectored interrupt controller (VIC 2.21 General purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.22 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.23 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.24 External Port Controller (EXPI I/ Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2/95 Power saving system mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Doc ID 16259 Rev 2 SPEAr600 ...
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... SPEAr600 3.1 Required external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2 Pin descriptions listed by functional block . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3 Configuration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.3.8 4 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.2 Maximum power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.3 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.4 Overshoot and undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5 ...
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... NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 16-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 GMII Transmit timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 MII transmit timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 GMII-MII Receive timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . 82 MDIO timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 SMI timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 SPI master mode timings (CPHA = SPI master mode timings (CPHA = Doc ID 16259 Rev 2 SPEAr600 ...
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... SPEAr600 List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. System reset, master clock, RTC and configuration pins . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 3. Power supply pins Table 4. Debug pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 5. SMI, SSP, UART, FIRDA and I2C pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 6. USB pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 7. Ethernet pins Table 8. GPIO pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 9. ADC pins Table 10 ...
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... Timing requirements for SPI mode on MOSI pad [CPHA = Table 58. Timing requirements for SPI mode on MISO pad [CPHA = Table 59. Timing requirements for SPI mode on MOSI pad [CPHA = Table 60. PBGA420 ( 2.06 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 61. Thermal resistance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 62. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6/95 Doc ID 16259 Rev 2 SPEAr600 ...
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... SPEAr600 List of figures Figure 1. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. Typical system architecture using SPEAr600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 3. Power on reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 4. DDR2 read cycle waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 5. DDR2 read cycle path Figure 6. DDR2 write cycle waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 7. DDR2 write cycle path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 8. DDR2 command waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 9 ...
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... Description 1 Description The SPEAr600 is a member of the SPEAr family of embedded MPUs for networked devices based on dual ARM926EJ-S processors (up to 333 MHz), widely used in applications where high computation performance is required. Both processors have an MMU supporting virtual memory management and making the system compliant with the Linux operating system. They also offer 16 KBytes of data cache, 16 KBytes of instruction cache, JTAG and ETM (embedded trace macro-cell) for debug operations ...
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... SPEAr600 1.1 Main features ● Dual core ARM926EJ-S 32-bit RISC CPU 333 MHz, each with: – 16 Kbytes of instruction cache, 16 Kbytes of data cache – 3 instruction sets: 32-bit for high performance, 16-bit (Thumb) for efficient code density, byte Java mode (Jazelle™) for direct execution of Java code. ...
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... ETM functionality multiplexed on primary pins. ● Supply voltages – 1.0 V core, 1.8 V/2.5 V DDR, 2.5 V PLLs 1.8 V RTC and 3.3 V I/Os ● Operating temperature °C ● ESD rating: HBM class 2, CDM class II ● PBGA420 ( 2.06 mm, pitch 1 mm) 10/95 Doc ID 16259 Rev 2 SPEAr600 ...
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... DDR2 DDR1 Debug, Trace The core of the SPEAr600 is the dual ARM926EJ-S reduced instruction set computer (RISC) processor. It supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to trade off between high performance and high code density and includes features for efficient execution of Java byte codes ...
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... Kbytes of SRAM 2.2 DDR/DDR2 memory controller SPEAr600 integrates a high performance multi-channel memory controller able to support DDR1 and DDR2 double data rate memory devices. The multi-port architecture ensures that memory is shared efficiently among different high-bandwidth client modules. 12/95 Doc ID 16259 Rev 2 ...
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... Two chip selects. – 16-bit data width 2.3 Serial memory interface SPEAr600 provides a Serial Memory Interface (SMI), acting as an AHB slave interface (32-, 16- or 8-bit) to SPI-compatible off-chip memories. These serial memories can be used either as data storage or for code execution. Main features: ● ...
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... Boot memory bank configurable at reset using external control pins. 2.5 Multichannel DMA controller Within its basic subsystem, SPEAr600 provides a DMA controller (DMAC) able to service independent DMA channels for serial data transfers between a single source and destination (i.e., memory-to-memory, memory-to-peripheral, peripheral to-memory, and peripheral-to-peripheral) ...
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... Each input/output can be controlled in two distinct modes: ● Software mode, through an APB interface ● Hardware mode, through a hardware control interface. SPEAr600 provides GPIO lines: ● Individually programmable input/output pins (default to input at reset) ● Hardware control capability of GPIO lines for different system configurations – ...
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... Hardware over sampling and accumulation up to 128 samples ● Eight analog input (AIN) channels, ranging from 0 to 2.5 V ● INL ± 1 LSB, DNL ± 1 LSB ● Programmable conversion speed, (min. conversion time is 1 µs) ● Programmable averaging of results from 1 (No averaging 128 16/95 Doc ID 16259 Rev 2 SPEAr600 ...
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... Power Management Module (PMT) with Remote Wake-up and Magic Packet frame processing options 2.11 USB2 host controller SPEAr600 has two fully independent USB 2.0 hosts. Each consists of 5 major blocks: ● EHCI capable of managing high-speed transfers (HS mode, 480 Mbps) ● OHCI that manages the full and the low speed transfers (12 and 1.5 Mbps) ● ...
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... AHB bus ● A USB plug detect (UPD) which detects the connection of a cable. 2.13 Synchronous Serial Peripheral (SSP) The SPEAR600 has three Synchronous Serial Peripherals (SSPs) (SPI, Microwire or TI protocol). Main features: ● Maximum speed of 40 Mbps ● ...
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... Separate 16x8 (16 locations deep x 8 bits wide) transmit and receive FIFOs to reduce CPU interrupts ● Speed up to 460.8 kbps 2.16 Fast IrDA controller The SPEAr600 has a Fast IrDA controller. Main features: ● Supports the following standards: – IrDA serial infrared physical layer specification (IrPHY), version 1.3 – ...
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... Watchdog module clock enable 2.18.1 Power saving system mode control Using three mode control bits, the system controller switch the SPEAr600 to any one of four different modes: DOZE, SLEEP, SLOW and NORMAL. ● SLEEP mode: In this mode the system clocks, HCLK and CLK, are disabled and the System Controller clock SCLK is driven by a low speed oscillator (nominally 32768 Hz) ...
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... PCBs, metal shielding and so on. This gives the customer appreciable cost savings. In sleep mode the SPEAr600 runs with the PLL disabled so the available frequency is 24 MHz or a sub-multiple (/2, /4, /8). PLL3 is used to generate the USB controller clocks and it is not configured through registers ...
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... Each GPT consists of 2 channels, each one made programmable 16-bit counter and a dedicated 8-bit timer clock prescaler. The programmable 8-bit prescaler performs a clock division 256, and different input frequencies can be chosen through SPEAr600 configuration registers (frequencies MHz can be synthesized). Two different modes of operation are available: ● ...
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... External Port Controller (EXPI I/f) The port controller is a socket communication interface between the SPEAr600 and an external FPGA device; it implements a simple AHB bidirectional protocol used to compress a couple of std AHB master/slave bus onto 84 PL_GPIOs and 4 PL_CLKs primary signals. ST provide a symmetric port controller logic solution to be embedded inside the external ...
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... Pin description 3 Pin description The following tables describe the pinout of the SPEAr600 listed by functional block. This description refers to the default configuration of SPEAr600 (full features). More details on the configuration of each pin are given in ● Table 2: System reset, master clock, RTC and configuration pins ● ...
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... SPEAr600 Table 2. System reset, master clock, RTC and configuration pins (continued) Group Signal name MCLK_XI Master clock MCLK_XO RTC_XI RTC RTC_XO Table 3. Power supply pins Group DIGITAL GROUND ANALOG GROUND I/O CORE HOST1/HOST2 USB PHY HOST2 USB PHY Ball Direction Y1 Input ...
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... For DDRI the supply voltage must be 2.5 V, instead for DDRII the supply voltage must be 1.8 V. 26/95 Signal name USB_HOST1_VDDBC USB_HOST1_VDDBS USB_DEV_VDDBC USB_DEV_VDDBS USB_DEV_VDD3V3 USB_PLL_VDDP USB_PLL_VDDP2V5 MCLK_VDD MCLK_VDD2V5 DITH_VDD2V5 DITH_VDD SSTL_VDDE1V8 U7, U8, U9, U11, U12, U14, U15 ADC_AVDD DDR_MEM_PLL_VDD_ANA DDR_MEM_PLL_VDD_DIG LVDS_VDDE2V5 RTC_VDDE_1V8 Doc ID 16259 Rev 2 SPEAr600 Ball Value 2.5 V AA1 1.0 V AA2 2 ...
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... SPEAr600 Table 4. Debug pins Group Signal name SSP_2_SS_1 DEBUG 1. This signal is part of the debug group and not the SSP group used for boot mode selection. Table 5. SMI, SSP, UART, FIRDA and I2C pins Group SMI_DATAOUT SMI Ball K18 TEST_0 E15 TEST_1 ...
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... V capable, 4mA buffer, 3.3 V Input Serial data in tolerant, PU Serial data I/O in/out capable, 4 mA, 3.3 V tolerant, I/O Serial clock SPEAr600 Pin type TTL bidir capable, 8 mA, (1) PU TTL output TTL input TTL output TTL input TTL bidir buffer, 3.3V ...
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... SPEAr600 Table 6. USB pins Group Signal name USB_DEV_DP USB_DEV_DM USB_DEV_VBUS USB_HOST1_DP USB_HOST1_DM USB_HOST1_VBUS USB USB_HOST1_OVRC USB_HOST2_DP USB_HOST2_DM USB_HOST2_VBUS USB_HOST2_OVRC USB_USB_RREF Ball Direction V1 USB Device D+ I/O V2 USB Device D- R4 Input T1 I/O T2 USB HOST1 D- P5 Output P6 Input P1 I/O P2 USB HOST2 D- R5 Output R6 Input ...
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... A18 A19 A17 Collision detect Input B17 Carrier sense Management B18 I/O Management C18 Output Doc ID 16259 Rev 2 SPEAr600 Function Pin type TTL output buffer, 3.3 V capable, (GMII Ext. Clock TTL input buffer, 3.3 V tolerant, PD MII TTL output buffer, 3.3 V capable TTL bidirectional buffer, 3 ...
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... SPEAr600 Table 8. GPIO pins Group Signal name GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 1. When the pin is not driven, the output voltage is 2 the core side, logic ‘1’ state is guaranteed. Table 9. ADC pins Group Signal name ...
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... Read enable H20 Write enable Output Address latch H21 Command latch G21 J18 Write protect H22 Input Doc ID 16259 Rev 2 SPEAr600 Function Pin Type TTL bidirectional buffer, 3.3 V capable, Data 4 mA, 3.3 V tolerant, (1) PU Chip enable TTL output buffer, 3.3 V capable, ...
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... SPEAr600 Table 11. DDR I/F pins Group Signal name DDR_ADD_0 DDR_ADD_1 DDR_ADD_2 DDR_ADD_3 DDR_ADD_4 DDR_ADD_5 DDR_ADD_6 DDR_ADD_7 DDR_ADD_8 DDR_ADD_9 DDR_ADD_10 DDR_ADD_11 DDR_ADD_12 DDR_ADD_13 DDR_ADD_14 DDR_BA_0 DDR_BA_1 DDR I/F DDR_BA_2 DDR_RAS DDR_CAS DDR_WE DDR_CLKEN DDR_CLK_P DDR_CLK_N DDR_CS_0 DDR_CS_1 DDR_ODT_0 DDR_ODT_1 DDR_DATA_0 DDR_DATA_1 DDR_DATA_2 ...
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... Ref. voltage Analog, see Ref Ext. ref resistor Common return - for Ext. resistors Analog, see Ref Ext. ref. resistor TTL input buffer, Input Configuration 3.3 V tolerant, PU SPEAr600 Pin type SSTL_2 SSTL_2/ SSTL_2/ SSTL_2/ SSTL_2/ Analog Note 2 on page 24 Power Note 1 on page 24 ...
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... SPEAr600 Table 12. LCD I/F pins Group Signal name CLD_0 CLD_1 CLD_2 CLD_3 CLD_4 CLD_5 CLD_6 CLD_7 CLD_8 CLD_9 CLD_10 CLD_11 CLD_12 CLD_13 CLD_14 CLD_15 CLD_16 LCD I/F CLD_17 CLD_18 CLD_19 CLD_20 CLD_21 CLD_22 CLD_23 CLAC CLCP CLFP CLLP CLLE CLPOWER Ball ...
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... PH2 A15 B15 PH3 A14 B14 PH4 C14 C13 PH5 A13 B13 PH6 A12 B12 PH7 C12 C11 PH8 A11 B11 Doc ID 16259 Rev 2 Direction Function Output General purpose I/O With LVDS transceiver Input LVDS Receiver SPEAr600 Pin Type LVDS Driver ...
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... SPEAr600 Table 14. EXPI/I2S pins Group Signal name PL_GPIO_47/ ADO_REC_DIN PL_GPIO_48/ ADO_REC_WS PL_GPIO_50/ ADO_WS_OUT PL_GPIO_51/ ADO_DOUT2 PL_GPIO_52/ ADO_DOUT1 EXPI/I2S PL_GPIO_53/ ADO_CLK_in_529 PL_GPIO_54/ MCLK_out_309 PL_GPIO_55/ ADO_RECORD_CLK PL_CLK_4/ ADO_CLK_OUT 1. When the pin is not driven, the output voltage is 2 the core side, logic ‘1’ state is guaranteed. ...
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... PL_GPIO_13 PL_GPIO_14 PL_GPIO_15 EXPI PL_GPIO_16 PL_GPIO_17 PL_GPIO_18 PL_GPIO_19 PL_GPIO_20 PL_GPIO_21 PL_GPIO_22 PL_GPIO_23 PL_GPIO_24 PL_GPIO_25 PL_GPIO_26 PL_GPIO_27 PL_GPIO_28 PL_GPIO_29 PL_GPIO_30 PL_GPIO_31 38/95 Ball Direction I Doc ID 16259 Rev 2 SPEAr600 Function Pin Type TTL bidirectional buffer 3.3 V capable, Logic I/O 3.3 V tolerant, 4 mA, (1) PU ...
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... SPEAr600 Table 15. EXPI pins (continued) Group Signal name PL_GPIO_32 PL_GPIO_33 PL_GPIO_34 PL_GPIO_35 PL_GPIO_36 PL_GPIO_37 PL_GPIO_38 PL_GPIO_39 PL_GPIO_40 PL_GPIO_41 PL_GPIO_42 PL_GPIO_43 EXPI PL_GPIO_44 PL_GPIO_45 PL_GPIO_46 PL_GPIO_49 PL_GPIO_56 PL_GPIO_57 PL_GPIO_58 PL_GPIO_59 PL_GPIO_60 PL_GPIO_61 PL_GPIO_62 PL_GPIO_63 Ball Direction I Doc ID 16259 Rev 2 Pin description Function ...
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... When the pin is not driven, the output voltage is 2 the core side, logic ‘1’ state is guaranteed 40/95 Ball Direction I E10 D10 C10 A7 Logic External A6 A5 Doc ID 16259 Rev 2 SPEAr600 Function Pin Type TTL bidirectional buffer 3.3 V capable, Logic I/O 3.3 V tolerant, 4 mA, (1) PU TTL bidirectional buffer, 3.3 V capable, 8 mA, Clock 3.3 V tolerant, (1) PU ...
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... UART extension for modem flow control ● Eight additional GPIOs ● One additional SMI chip select (please refer to section 17.8.1 in the SPEAr600 user manual for more details). 3.3.3 Disable LCD ctr The Color LCD controller interface is disabled and alternatively the following features are provided: ● ...
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... Two UARTs : one with extension for modem flow control and one with simplified hardware flow control ● One additional SMI chip select (please refer to section 17.8.1 in the SPEAr600 user manual for more details). ● Four additional clocks programmable trough the GPT registers. Please refer to the SPEAr600 user manual (UM0510) for more details ...
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Table 16. Multiplexing scheme Ball Mode 0 Mode 1 W11 AIN_0 V11 AIN_1 V12 AIN_2 W12 AIN_3 W13 AIN_4 V13 AIN_5 V14 AIN_6 W14 AIN_7 W15 ADC_VREFN V15 ADC_VREFP W18 GPIO_0 V18 GPIO_1 U18 GPIO_2 T18 GPIO_3 W19 GPIO_4 V19 ...
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Table 16. Multiplexing scheme (continued) Ball Mode 0 Mode 1 AB22 SSP_1_SCLK AB21 SSP_1_MISO AA21 SSP_1_MOSI AA22 SSP_1_SS Y20 CLD_0 Y21 CLD_1 Y22 CLD_2 W22 CLD_3 W21 CLD_4 W20 CLD_5 V20 CLD_6 V21 CLD_7 V22 CLD_8 U22 CLD_9 U21 CLD_10 ...
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Table 16. Multiplexing scheme (continued) Ball Mode 0 Mode 1 T22 CLAC R22 CLCP P22 CLFP M22 CLLE N22 CLLP M19 CLPOWER L21 SMI_DATAIN L20 SMI_DATAOUT L22 SMI_CLK L19 SMI_CS_0 L18 SMI_CS_1 K22 SSP_2_SCLK K21 SSP_2_MISO K20 SSP_2_MOSI K18 SSP_2_SS_1 ...
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Table 16. Multiplexing scheme (continued) Ball Mode 0 Mode 1 G20 NF_CE nUART1RTS H20 NF_WE nUART1CTS G22 NF_RE nUART1DCD H21 NF_ALE nUART1DTR G21 NF_CLE nUART1DSR H22 NF_RB nUART1RI J18 NF_WP SMICS_OUT_3 C17 MRESET D11 DDR2_EN D17 nTRST E16 TCK D15 ...
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Table 16. Multiplexing scheme (continued) Ball Mode 0 Mode 1 D20 GMII_TXD_5 C22 GMII_TXD_6 C21 GMII_TXD_7 D19 TX_EN D18 TX_ER A22 RX_CLK C19 RX_DV C20 RX_ER B22 RXD_0 B21 RXD_1 A21 RXD_2 B20 RXD_3 A20 GMII_RXD_4 B19 GMII_RXD_5 A18 GMII_RXD_6 ...
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Table 16. Multiplexing scheme (continued) Ball Mode 0 Mode 1 B15 PH2n A14 PH3 B14 PH3n C14 PH4 C13 PH4n A13 PH5 B13 PH5n A12 PH6 B12 PH6n C12 PH7 C11 PH7n A11 PH8 B11 PH8n B9 RTC_XO A9 RTC_XI ...
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Table 16. Multiplexing scheme (continued) Ball Mode 0 Mode 1 D8 PL_GPIO_74 E8 PL_GPIO_73 B7 PL_GPIO_72 C7 PL_GPIO_71 D7 PL_GPIO_70 E7 PL_GPIO_69 F7 PL_GPIO_68 F6 PL_GPIO_67 E6 PL_GPIO_66 D6 PL_GPIO_65 C6 PL_GPIO_64 B6 PL_GPIO_63 B5 PL_GPIO_62 C5 PL_GPIO_61 D5 PL_GPIO_60 ...
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Table 16. Multiplexing scheme (continued) Ball Mode 0 Mode 1 D1 PL_GPIO_46 D2 PL_GPIO_45 D3 PL_GPIO_44 E1 PL_GPIO_43 E2 PL_GPIO_42 E3 PL_GPIO_41 E4 PL_GPIO_40 F1 PL_GPIO_39 F2 PL_GPIO_38 F3 PL_GPIO_37 F4 PL_GPIO_36 F5 PL_GPIO_35 G5 PL_GPIO_34 G4 PL_GPIO_33 G3 PL_GPIO_32 ...
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Table 16. Multiplexing scheme (continued) Ball Mode 0 Mode 1 K2 PL_GPIO_18 K3 PL_GPIO_17 K4 PL_GPIO_16 K5 PL_GPIO_15 K6 PL_GPIO_14 L5 PL_GPIO_13 L4 PL_GPIO_12 L3 PL_GPIO_11 L2 PL_GPIO_10 L1 PL_GPIO_9 M1 PL_GPIO_8 M2 PL_GPIO_7 M3 PL_GPIO_6 M4 PL_GPIO_5 M5 PL_GPIO_4 ...
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Table 16. Multiplexing scheme (continued) Ball Mode 0 Mode 1 V1 USB_DEV_DP V2 USB_DEV_DM U4 USB_USB_RREF Y2 MCLK_XO Y1 MCLK_XI Table 17. Table shading Shading GPIO UART SMI GPT TEST Mode 2 Mode 3 Mode 4 USB_DEV_DP USB_DEV_DM USB_USB_RREF MCLK_XO ...
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... SPEAr600 4 Memory map Table 18. Memory map Start address 0x0000.0000 0x4000.0000 0x4000.0800 0x4000.0821 0xC000.0000 0xCFFF.F800 0xD000.0000 0xD008.0000 0xD010.0000 0xD018.0000 0xD020.0000 0xD028.0000 0xD080.0000 0xD100.0000 0xD180.0000 0xD200.0000 0xD280.0000 0xD300.0000 0xD800.0000 0xD808.0000 0xD810.0000 0xD818.0000 0xD820.0000 0xD828.0000 0xE000.0000 0xE080.0000 0xE100.0000 0xE110.0000 0xE120.0000 0xE130.0000 0xE180.0000 End address Peripheral 0x3FFF ...
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... SDRAM Controller 0xFC87.FFFF Timer 1 0xFC8F.FFFF Watchdog Timer 0xFC97.FFFF Real time Clock 0xFC9F.FFFF General Purpose I/O 0xFCA7.FFFF System Controller 0xFCAF.FFFF Miscellaneous Registers 0xFEFF.FFFF - 0xFFFF.FFFF Internal ROM Doc ID 16259 Rev 2 SPEAr600 Description Reserved Reserved Configuration register Reserved Reserved Reserved Reserved Reserved Boot ...
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... SPEAr600 5 Electrical characteristics 5.1 Absolute maximum ratings This product contains devices to protect the inputs against damage due to high/low static voltages. However it is advisable to take normal precaution to avoid application of any voltage higher/lower than the specified maximum/minimum rated voltages. The Absolute maximum rating is the maximum stress that can be applied to a device without causing permanent damage ...
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... Parameter Supply voltage at 1.0 Supply voltage at 3.3 Supply voltage at 2.5 Supply voltage at 1.8 Supply voltage at 1.8 Operating temperature Parameter Amplitude Doc ID 16259 Rev 2 SPEAr600 Min Typ Max Unit 0. 3.3 3 ...
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... SPEAr600 5.5 3.3V I/O characteristics The 3.3 V I/Os are compliant with JEDEC standard JESD8b Table 23. Low voltage TTL DC input specification (3 V< V Symbol Vhyst Table 24. Low voltage TTL DC output specification (3 V< V Symbol V Low level output voltage OL V High level output voltage OH 1. For the max current value (X mA) refer to Table 25 ...
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... OSCI 30MHz resets_o sclk npor_o hresetn arm_fetching pll_lock 58/95 Parameter termination termination Parameter Voltage applied to core/pad All Vdd are stable synch 10 ms 2.95 us Doc ID 16259 Rev 2 SPEAr600 Min. Typ. Max Unit 75 150 Min. Typ. Max Unit 0.49 * 0.500 * 0. DDE DDE DDE ...
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... SPEAr600 Note: 1 The oscillator generates a stable clock 1.5 ms after the power supply becomes stable. 2 The Pll lock time is given by the following formula: Lock time = (decimal equivalent of PLL charge pump bit setting + 1) The PLL charge pump (CP) bits are in the PLL1/2_CTR register in the Miscellaneous register block ...
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... DLL t3 (t1 + t2) MAX MIN 133 ps 212 ps 134 ps 205 ps 336 ps 611 ps 348 ps 550 ps Frequency 333 MHz 266 MHz Doc ID 16259 Rev 2 SPEAr600 = 125 °C and in best case SET D t2 CLR t3 (t1 + t2) MIN 125 ps 244 ps 127 ps 239 ps 311 ps 646 ps 324 ps 590 MAX ...
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... SPEAr600 Table 32. DDR2 read cycle timings without pad delay (continued) Period ( 7.5 ns Table 32 shows the internal chip timing without the contribution of the pads. These values are obtained considering the nominal setting of DLL at T/4 period, in fact, the DDR memory launches data (DQ) and data strobe (DQS) aligned. Internally the DQS is delayed by T/4 (DLL) to guarantee correct data capture ...
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... DQS edges are centered of the data that can be defined as the time range where the SETUP Doc ID 16259 Rev (t1 + t2) MIN MIN 1.91 ns 1.95 ns 5 MIN 396 ps 492 ps 585 ps 681 ps 895 ps 991 ps 1.15 ns 1.25 ns 1.52 ns 1.62 ns SPEAr600 DQS DQ MAX 2.13 ns 2.15 ns 5.33 ns 5.35 ns MIN ...
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... SPEAr600 data are stable before the arrival of the DQS. To have a positive quantity the delay obtained by the DQ (maximum delay or last variation) must be less than one obtained by the DQS (minimum delay). So DQS (delay) MIN ± one DLL element t5 can be expressed in a similar way, and can be defined as the t ...
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... MIN Frequency 333 MHz 266 MHz 200 MHz 166 MHz 133 MHz Doc ID 16259 Rev (T T MIN MAX MAX of the commands: HOLD ) - ( T MIN MAX t4 t5 MIN MIN 977 ps 1.33 ns 1.35 ns 1.71 ns 1.98 ns 2.33 ns 2.49 ns 2.84 ns 3.23 ns 3.59 ns SPEAr600 + t3 MIN MAX ...
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... SPEAr600 6.2 EXPI timing characteristics The characterization timing is done for an output load PL_CLKx and PL_GPIO_x .The operating conditions are in worst case V=0. =125 °C and in best case V=1.10 V TA= 40 °C. The timings are measured using TEST [5:0] = 101xxx: (Selg_cfg5 = EXPI with internal clock) ...
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... Out. Out. Inp. Inp. Out. Out. Inp. Bidir. Bidir. Inp. Out. SET SET ck_ff Doc ID 16259 Rev 2 SPEAr600 PL_GPIOs signal assignment PL_GPIO_37 PL_GPIO_38 PL_GPIO_39 PL_GPIO_40 PL_GPIO(42:41) PL_GPIO_43 PL_GPIO_44 PL_GPIO_45 PL_GPIO_46 PL_GPIO(48:47) PL_GPIO(50:49) PL_GPIO(52:51) PL_GPIO(54:53) PL_GPIO_83 PL_CLK_1 PL_CLK_2 PL_CLK_3 PL_CLK_4 PL_GPIO LK1 ...
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... SPEAr600 Figure 12. EXPI signal timing waveforms PL_ CLK1 Input PL _GPIO[ x] Output Table 37. EXPI clock and reset parameters Parameter CLK period Tf CLK fall Tr CLK rise Signals Reset Table 38. SOC-master Signals HADDR HSIZE,HWRITE, HBURST, HTRANS, HMASTLOCK, HSEL, HReady_in (45) HWDATA HReady_out(44), HRESP HRDATA I Table 39. ...
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... CK_PAD(min) CK_FF )(max (min) CK_FF CK_PAD )(min (max) CK_PAD and t are taken the maximum value from worst case and best case, max . min Q SET SET t ck_ ck_pad Doc ID 16259 Rev 2 -1.94 -1.94 t (ns) max 4.21 7.34 CK_FF out Q SPEAr600 PL_GPIO[x] PL_CLK1 ...
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... SPEAr600 Figure 14. EXPI signal timing waveforms PL_ CLK1 Input PL _GPIO [x] Output Table 40. Clock and Reset Parameter CLK period Tf CLK fall Tr CLK rise Output Signals Reset Table 41. SOC-master Signals HADDR HSIZE,HWRITE, HBURST, HTRANS, HMASTLOCK, HSEL, HReady_in (45) HWDATA HReady_out(44), HRESP HRDATA Table 42. ...
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... Timing characteristics Table 42. SOC-slave (continued) HGRANT, HReady_mst(43), HRESP HRDATA 70/95 Input Output Tmin(ns) 3.11 2.68 Doc ID 16259 Rev 2 SPEAr600 Tmax(ns) 10.61 13.74 ...
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... SPEAr600 6.3 CLCD timing characteristics The characterization timing is done considering an output load all the outputs.The operating conditions are in worst case V=0.90 V T=125 °C and in best case V=1. °C. The CLCD has a wide variety of configurations and setting and the parameters change accordingly. Two main scenarios will be considered, one with direct clock to output (166 MHz), setting BCD bit to '1', and the second one with the clock passing through a clock divider (83 MHz), setting BCD bit to '0' ...
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... Tclock divided max rise (Tr) Tclock divided max (Tf) Tmin Tmax Tstable 72/95 Tclock Tmax Tmin Tstable D SET Q Q CLR SET CLR Value 12 ns 0.81 ns 0.87 ns -0.49 ns 2.38 ns 9.13 ns Doc ID 16259 Rev 2 SPEAr600 Tf CLD[23:0], CLAC, CLLE, CLLP, CLFP, CLPOWER t2 CLCP t3 Frequency 83.3 MHz Tr ...
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... SPEAr600 Note: 1 Tstable = Tclock direct max - (Tmax + Tmin) 2 For Tmax the maximum value is taken from the worst case and for Tmin the minimum value is taken from the best case. 3 CLCP should be delayed by {Tmax + [Tclock direct max - (Tmax + Tmin)]/2} = 6.945 ns 6.4 I2C timing characteristics The characterization timing is given for an output load SCL and SDA. The operating conditions are V=0.90 V, T=125 ° ...
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... C in fast-speed mode Parameter standard-speed mode Parameter Doc ID 16259 Rev -STO Min 163.31 ns 487.73 ns 313.38 ns 7.04 ns 642.98 ns 4.74 µs Min 643.27 ns 601.73 ns 1.19 µs 7.04 ns 642.98 ns 4.74 µs Min 4.73 µs 3.99 µs 4.67 µs 7.04 ns 4.03 µs 4.74 µs SPEAr600 STO ...
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... I2C Bus Specification v3-0 Jun 2007). However, the SDA data hold time in the I2C controller of SPEAr600 is one-clock cycle based (7 ns with the HCLK clock at 166 MHz). This time may be insufficient for some slave devices. A few slave devices may not receive the valid address due to the lack of SDA hold time and will not acknowledge even if the address is valid ...
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... Figure 24. Input pads for 8-bit NAND Flash configuration NFRB NFIO_0..7 Figure 25. Output command signal waveforms for 8-bit NAND Flash configuration NFCE NFCLE NFWE NFIO 76/95 SET CLR ... ... SET CLR HCLK T CLE Command Doc ID 16259 Rev 2 SPEAr600 NFCLE NFCE NFWE ... NFRE NFRWPRT NFALE NFIO_0..7 SET CLR D SET Q Q CLR ...
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... SPEAr600 Figure 26. Output address signal waveforms for 8-bit NAND Flash configuration NFCE NFALE NFWE NFIO Figure 27. In/out data address signal waveforms for 8-bit NAND Flash configuration NFCE NFWE NFIO (out) NFRE NFIO (in) Table 48. Time characteristics for 8-bit NAND Flash configuration Parameter ...
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... Figure 30. Output command signal waveforms 16-bit NAND Flash configuration NFCE NFCLE NFWE NFIO 78/95 SET CLR ... ... SET CLR HCLK ... (NFIO_8..15) T CLE Command Doc ID 16259 Rev 2 SPEAr600 NFCLE NFCE NFWE NFRE NFRWPRT NFALE NFIO_0..7 CLPOWER ... CLLP CLLE (NFIO_8..15) CLFP CLCP CLAC CLD_23..22 SET CLR ... D SET Q Q CLR ...
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... SPEAr600 Figure 31. Output address signal waveforms 16-bit NAND Flash configuration NFCE NFALE NFWE NFIO Figure 32. In/out data signal waveforms for 16-bit NAND Flash configuration (in ) Table 49. Time characteristics for 16-bit NAND Flash configuration Parameter TCLE TALE TWE (s=1) TRE (s=1) TIO (h=1) ...
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... Tclock Parameter Value using GMII [t value for the PHY you have to consider the next t SETUP SETUP Doc ID 16259 Rev TXD [0..3] TX_CLK period = 8 ns 125 MHz] CLK <1 ns <1 ns 2.8 ns 0.4 ns 5.19 ns rising edge, so CLK = CLK max SPEAr600 Tr ...
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... SPEAr600 6.6.2 MII transmit timing specifications Figure 35. MII TX waveforms TX_CLK Tmax Tmin TXD0-TXD3 Figure 36. Block diagram of MII TX pins TX[0..3] Table 51. MII TX timings Parameter max max min min min max t SETUP Note: To calculate the t you have to apply the following formula: t Tclock D SET ...
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... The receive path is optimized for the GMII interface: this also ensures correct capture of data for the MII10/100 interface. 6.6.4 MDIO timing specifications Figure 39. MDC waveforms MDC Input MDIO Output 82/95 Tclock Ts RX[0..3], GMII_RX[4..7], RX_ER, RX_DV t1 Tclock Tsetup Tmax Tmi n Doc ID 16259 Rev SET Q Q CLR SETUP Thold Tf SPEAr600 Tr and t HOLD Tr ...
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... SPEAr600 Figure 40. Paths from MDC/MDIO pads INPUT CLK Table 52. MDC/MDIO timing Parameter t period CLK t fall (t ) CLK f t rise (t ) CLK max CLK min CLK SETUPmax max HOLDmin min Note: When MDIO is used as output the data are launched on the falling edge of the clock as ...
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... Doc ID 16259 Rev 2 =125° C and in best A Thold T f Trmin Trmax SMI_DATAIN SMI_CLK SMI_DATAOUT SMI_CS_n (n= 0,1,3) Description SMI period (normal mode). SMI period (fast read mode). Transition times. Max setup time and min hold time of data in, referred to SMI_CLK rising edge. SPEAr600 Tr ...
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... SPEAr600 Table 53. SMI timings in default configuration (continued) Signal SMI_DATAOUT SMI_CS_0 SMI_CS_1 Table 54. SMI Timings of SMI_CS_3 in non-default configurations Signal NF_WP (SMI_CS_3 in Disable_nand_flash) CLD_14 (SMI_CS_3 in Disable_LCD_ctr) RX_ER (SMI_CS_3 in Disable_GMAC_ctr) Parameter Value t 0.65 ns Max and min delay time of data out, max referred to SMI_CLK falling edge. ...
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... Programmable Clock Polarity (CPOL) and Clock Phase (CPHA) The following Tables show the Timing Requirements of the SPI four-wire synchronous transfer for the 3 SSP modules present in the Spear600 configured in master mode (indicated in the tables as SPI1, SPI2 and SPI3). Both the Timings on MISO (master input slave output) pad and MOSI (master output slave input) pad are provided ...
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... SPEAr600 The Motorola SPI interface is a four-wire interface where SSP_SS signal behaves as a slave select. The main feature of the Motorola SPI format is that the inactive state and phase of the output clock signal are programmable through the CPOL (clock polarity) and CPHA (clock phase) parameters inside an IP control register. ● ...
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... SSP_SCLK (output) falling edge Setup time, MISO (input) 5 valid before SSP_SCLK (output) rising edge 88/95 parameters CPOL parameters CPOL 0 1 Doc ID 16259 Rev 2 SPI1 SPI2 SPI3 T T/2 SPI1 SPI2 SPI3 9.632 10.804 10.427 9.563 10.759 10.357 SPEAr600 unit ns ns unit ns ns ...
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... SPEAr600 Table 58. Timing requirements for SPI mode on MISO pad [CPHA = 1] (continued) No Hold time, MISO (input) 6 valid after SSP_SCLK (output) falling edge Hold time, MISO (input) 7 valid after SSP_SCLK (output) rising edge Table 59. Timing requirements for SPI mode on MOSI pad [CPHA = 1] No ...
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... Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK trademark. SPEAr600 is ROHS-6 compliant. 90/95 Doc ID 16259 Rev 2 SPEAr600 ® ...
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... SPEAr600 7.1 Package mechanical data Table 60. PBGA420 ( 2.06 mm) mechanical data Dim ddd eee fff mm Min. Typ. Max. 2.06 0.24 0.56 0.97 1.53 0.40 0.50 0.60 22.80 23.00 23.20 21.00 20.00 22.80 23.00 23.20 21.00 20.00 1.00 1.00 0.20 0.25 0.10 Doc ID 16259 Rev 2 ...
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... Package information Figure 46. PBGA420 ( 2.06 mm) package top view 92/95 Doc ID 16259 Rev 2 SPEAr600 ...
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... SPEAr600 Figure 47. PBGA420 ( 2.06 mm) package bottom view Table 61. Thermal resistance characteristics package PBGA420 Θ ( °C/ Doc ID 16259 Rev 2 Package information Θ ( °C/W) JB 18.5 93/95 ...
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... Updated Table 3: Power supply Updated Table 6: USB 2 Updated Figure 1: Functional block diagram system architecture using SPEAr600 Changed “SPI” with “SSP” where necessary. Inserted the new Section 6.8: SSP timing characteristics Corrected the frequency of DDR1. Separeted in two chapters the characteristics. ...
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... SPEAr600 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...