MCIMX512DJM8CR2 Freescale Semiconductor, MCIMX512DJM8CR2 Datasheet - Page 84

• Manufacturer Part Number: MCIMX512DJM8CR2
• Description: IC MPU I.MX51 529MABGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX51r

Specifications of MCIMX512DJM8CR2

• Core Processor: ARM Cortex-A8
• Core Size: 32-Bit
• Speed: 800MHz
• Connectivity: 1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 128
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.8 V ~ 1.15 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 529-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Electrical Characteristics
A frame starts with a rising edge on SENSB_VSYNC (all the timings correspond to straight polarity of the
corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is
valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.
SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops
receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the
SENSB_VSYNC timing repeats.
4.7.8.1.3
The timing is the same as the gated-clock mode (described in
except for the SENSB_HSYNC signal, which is not used. See
valid and cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states
low) until valid data is going to be transmitted over the bus.
The timing described in
different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC;
active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.
4.7.8.2
Figure 51
the IPU.
84
SENSB_DATA,
SENSB_VSYNC,
SENSB_HSYNC
SENSB_PIX_CLK
(Sensor Output)
SENSB_DATA[19:0]
depicts the sensor interface timing. SENSB_MCLK signal described here is not generated by
SENSB_PIX_CLK
SENSB_VSYNC
Electrical Characteristics
Non-Gated Clock Mode
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
Start of Frame
Figure 50
invalid
Figure 50. Non-Gated Clock Mode Timing Diagram
nth frame
Figure 51. Sensor Interface Timing Diagram
is that of a typical sensor. Some other sensors may have a slightly
1st byte
IP3
IP2
n+1th frame
Section 4.7.8.1.2, “Gated Clock
invalid
Figure
1/IP1
50. All incoming pixel clocks are
1st byte
Freescale Semiconductor
Mode”),