MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 9

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Signal group layout guidelines:
Freescale Semiconductor
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Data (DQx)
— Single ended, bi-directional, synchronized to data strobes, terminated on die with ODT.
— Registered on rising and falling edges of data strobe.
Data Strobes (DQSx)
— Differential, bi-directional, terminated on die with ODT.
— One differential pair for each byte lane.
DQS/DQ/DQM
— A data group (DQ) has an associated strobe (DQS) and data mask (DQM).
— All DQS/DQ/DQM groups should be length matched as closely as possible given layout and
— Overall length mismatch between byte lanes should be less than 500 mils.
Use a wide trace / plane if possible for VREF.
Address and Command signals
— Should be length matched to each other within 200 mils.
— Traces routed with a 50-60 ohms single ended impedance.
Data signals (DQx)
— All data signals within a byte lane length must be matched to within 100 mils of each other (the
— Lengths must be matched within 100 mils of the corresponding data strobes (the closer the
— Traces routed with a 50-60 ohms single ended impedance.
Data strobes (DQSx)
— 1 per byte lane.
— Clock pair length should be matched within 25 mils.
— Length must be matched within 100 mils of the corresponding data byte lane (the closer the
— 100 ohm +/- 10% differential impedance, 50-60 ohms single ended impedance on the
Data masks (DQMx)
— 1 per byte lane.
— Length must be matched within 100 mils of the corresponding data byte lane (the closer the
— Traces routed with a 50-60 ohms single ended impedance.
DRAM clock (EMI_CLK / EMI_CLKn)
— Clock pair lengths should be matched within 25 mils.
plac e m e nt cons traints to minimize skew within the group and across the channel.
closer the matching, the better).
matching, the better).
matching, the better).
individual traces.
matching, the better).
i.MX28 Layout and Design Guidelines, Rev. 0
DRAM Memory
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