MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 10

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

DRAM Memory
Other important guidelines:
5.3
If possible, keep the DRAM DATA, DQM, STROBE, and CLOCK traces short enough so that a maximum
of 30% of the edge appears on the trace. To put it in equation form:
The speed of a signal edge travelling from sender to receiver on widely used FR4 material is about 1/5 the
speed of light (or 15 cm/ns).
The full reflection occurs if the time for an edge travelling from sender (i.MX) to receiver (DRAM) is >=
the rise/fall time of the signal. Example:
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— 100 ohm +/- 10% differential impedance, 50-60 ohms single ended impedance on the
— During a write cycle, the i.MX28 must satisfy the timing specs between DQS and CK to
EMI_DDR_OPEN and EMI_DDR_OPEN_FB
— These pins are specific to the i.MX28 DRAM memory controller and must be connected
The DRAM DATA, DQM (data mask) and DQS (strobe) signals should use the same number of
vias and route on the same layers and number of layers.
Matching the numbers of vias and layers used is more important than matching the trace length.
Route all DRAM traces over a solid GND plane with no discontinuities or plane splits on the layers
adjacent to the DRAM traces (both above and below). It is important that the board designer
provide these signals with a solid reference plane to control the characteristic impedance and
provide a smaller loop area between the signals and the return currents. The EMI/DRAM power
plane can also be used as the reference/return plane, but the GND plane is preferred and has the
quietest return path for the signals.
Isolate and protect the VREF trace/plane from noise.
Keep data groups away from address and control signal lines to avoid cross talk.
DRAM traces should be routed at short as possible to reduce trace capacitance and minimize
reflections.
Trace Length <= (0.3 x Rise/Fall Time x 15 cm/ns).
If the rise/fall time = 0.5ns and trace length = 7.5cm, the receiver still sees zero volts even though
the sender is now driving at the maximum DRAM supply voltage. Because the full edge is now on
the line, full reflection occurs.
So for this example, the signal traces should not exceed 2.25cm (30% of 7.5cm). This is valid for
the distance between one sender and one receiver.
Minimizing Reflections
individual traces.
facilitate the reliable transfer of data. To satisfy the clock to strobe (DQS) relationship, it is
preferable that the clock length be between the shortest and longest strobe lengths.
together. The total routed length from one pin to the other needs to be the following:
– CLK routed distance + DQS routed distance
i.MX28 Layout and Design Guidelines, Rev. 0
Freescale Semiconductor