MCIMX281AVM4B Freescale Semiconductor, MCIMX281AVM4B Datasheet - Page 6

• Manufacturer Part Number: MCIMX281AVM4B
• Description: IC MPU I.MX28 1.2 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX281AVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 4
6
Mnemonic
APBHDMA
APBXDMA
AUART(5)
CLKCTRL
ARM9 or
ARM926
Block
BCH
DCP
BSI
describes the digital and analog modules of the device.
ARM926EJ-S
CPU
UART
interface
ECC
accelerator
Scan Interface
Clock control
module
Data
co-processor
Application
Bit-correcting
Boundary
AHB to APBH
AHB to APBX
Block Name
Bridge with
Bridge with
i.MX28 Applications Processors Data Sheet for Automotive Products, Rev. 0
DMA
DMA
System control The AHB to APBH bridge with DMA includes the AHB-to-APB PIO bridge for
System control The AHB-to-APBX bridge includes the AHB-to-APB PIO bridge for
ARM ®
Connectivity
peripherals
Connectivity
peripherals
Connectivity
peripherals
Clocks
Security
Subsystem
Table 4. i.MX28 Digital and Analog Modules
memory-mapped I/O to the APB devices, as well a central DMA facility for
devices on this bus. The bridge provides a peripheral attachment bus running
on the AHB’s HCLK. (The ‘H’ in APBH denotes that the APBH is synchronous
to HCLK, as compared to APBX, which runs on the crystal-derived XCLK.)
The DMA controller transfers read and write data to and from each peripheral
on APBH bridge.
memory-mapped I/O to the APB devices, as well a central DMA facility for
devices on this bus. The AHB-to-APBX bridge provides a peripheral
attachment bus running on the AHB’s XCLK. (The ‘X’ in APBX denotes that
the APBX runs on a crystal-derived clock, as compared to APBH, which is
synchronous to HCLK.) The DMA controller transfers read and write data to
and from each peripheral on APBX bridge.
The ARM926 Platform consists of the ARM926EJ-S™ core and the ETM
real-time debug modules. It contains the 16-Kbyte L1 instruction cache,
32-Kbyte L1 data cache, 128-Kbyte ROM and 128-Kbyte RAM.
Each of the UART modules supports the following serial data
transmit/receive protocols and configurations:
The Bose, Ray-Chaudhuri, Hocquenghem (BCH) Encoder and Decoder
module is capable of correcting from 2 to 20 single bit errors within a block of
data no larger than about 900 bytes (512 bytes is typical) in applications such
as protecting data and resources stored on modern NAND flash devices.
The boundary scan interface is provided to enable board level testing.
There are five pins on the device which is used to implement the IEEE Std
1149.1™ boundary scan protocol.
The clock control module, or CLKCTRL, generates the clock domains for all
components in the i.MX28 system. The crystal clock or PLL clock are the two
fundamental sources used to produce most of the clock domains. For lower
performance and reduced power consumption, the crystal clock is selected.
The PLL is selected for higher performance requirements but requires
increased power consumption. In most cases, when the PLL is used as the
source, a Phase Fractional Divider (PFD) can be programmed to reduce the
PLL clock frequency by up to a factor of 2.
This module provides support for general encryption and hashing functions
typically used for security functions. Because its basic job is moving data
from memory to memory, it also incorporates a memory-copy (memcopy)
function for both debugging and as a more efficient method of copying data
between memory blocks than the DMA-based approach.
• 7- or 8-bit data words, one or two stop bits, programmable parity (even,
• Programmable baud rates up to 3.25 MHz. This is a higher maximum
odd, or none)
baud rate than the 1.875 MHz specified by the TIA/EIA-232-F standard
and previous Freescale UART modules. 16-byte FIFO on Tx and 16-byte
FIFO on Rx supporting auto-baud detection
Brief Description
Freescale Semiconductor