AT32UC3C0512C-ALUT Atmel, AT32UC3C0512C-ALUT Datasheet - Page 67

• Manufacturer Part Number: AT32UC3C0512C-ALUT
• Description: IC MCU AVR32 512K FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3C0512C-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 123
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Data Bus Width: 32 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.9
7.9.1
Table 7-38.
Note:
7.9.2
Table 7-39.
32117A–10/2010
Parameter
Startup time from power-up, using
regulator
Startup time from reset release
Wake-up
Symbol
t
RESET
Timing Characteristics
1. These values are guaranteed by design and will be updated after characterization of current silicon.
Startup, Reset, and Wake-up Timing
RESET_N characteristics
Parameter
RESET_N minimum pulse length
Maximum Reset and Wake-up Timing
RESET_N Clock Waveform Parameters
Idle
Frozen
Standby
Stop
Deepstop
Static
The startup, reset, and wake-up timings are calculated using the following formula:
Where
another clock source than RCSYS is selected as CPU clock the startup time of the oscillator,
Please refer to the source for the CPU clock in the
more details about oscillator startup times.
t
t
OSCSTART
=
t
CONST
t
CONST
VDDIN_5 rising (TBD V/ms)
Time from VDDIN_5=0 to the first instruction
entering the decode stage of CPU. VDDCORE is
supplied by the internal regulator.
Time from releasing a reset source (except POR,
BOD18, and BOD33) to the first instruction entering
the decode stage of CPU.
From wake-up event to the first instruction of an
interrupt routine entering the decode stage of the
CPU.
Measuring
, must added to the wake-up time in the stop, deepstop, and static sleep modes.
+
N
and
CPU
×
N
CPU
t
CPU
Condition
(1)
are found in
Table
7-38.
2 * T
Min.
”Oscillator Characteristics” on page 56
RCSYS
t
CPU
Max
is the period of the CPU clock. If
Typ.
t
CONST
1240
TBD
TBD
TBD
TBD
0
0
0
(1)
Max.
(in µs)
AT32UC3C
clock cycles
Max
Units
TBD
TBD
TBD
TBD
TBD
TBD
N
0
0
CPU
for
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