AT32UC3C0512C-ALUT Atmel, AT32UC3C0512C-ALUT Datasheet
AT32UC3C0512C-ALUT
Specifications of AT32UC3C0512C-ALUT
Available stocks
Related parts for AT32UC3C0512C-ALUT
AT32UC3C0512C-ALUT Summary of contents
Page 1
... Flexible End-Point Configuration and Management with Dedicated DMA Channels – On-chip Transceivers Including Pull-Ups • One 2-channel Controller Area Network (CAN) – CAN2A and CAN2B protocol compliant, with high-level mailbox system ® Microcontroller ® 32-bit AVR Microcontroller AT32UC3C0512C AT32UC3C0256C AT32UC3C0128C AT32UC3C064C AT32UC3C1512C AT32UC3C1256C AT32UC3C1128C AT32UC3C164C AT32UC3C2512C AT32UC3C2256C ...
Page 2
Two independent channels, 16 Message Objects per Channel • One 4-Channel 20-bit Pulse Width Modulation Controller (PWM) – Complementary outputs, with Dead Time Insertion – Output Override and Fault Protection • Two Quadrature Decoders • One 16-channel 12-bit Pipelined ...
Page 3
Description The AT32UC3C is a complete System-On-Chip microcontroller based on the AVR32UC RISC processor running at frequencies MHz. AVR32UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular empha- sis on ...
Page 4
... The analog comparators can be paired to detect when the sensing voltage is within or outside the defined reference window. Atmel offers the QTouch library for embedding capacitive touch buttons, sliders, and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers ...
Page 5
Overview 2.1 Block diagram Figure 2- 32117A–10/2010 Block diagram aWire RESET_N TDO JTAG TCK NEXUS TDI INTERFACE TMS CLASS 2+ MEMORY PROTECTION UNIT MCKO OCD MDO[5..0] INSTR MSEO[1..0] INTERFACE EVTI_N EVTO_N VBUS D+ USB D- ...
Page 6
... SPI CAN channels USB Ethernet MAC 10/100 I2S Asynchronous Timers Timer/Counter Channels PWM channels QDEC Frequency Meter Watchdog Timer Power Manager Oscillators 12-bit ADC number of channels 12-bit DAC number of channels 32117A–10/2010 Configuration Summary AT32UC3C0512C/ AT32UC3C0256C/ AT32UC3C0128C/ AT32UC3C064C 512/256/128/64 KB 64/64/32/16KB 1 123 ...
Page 7
... Table 2-1. Feature Analog Comparators JTAG aWire Max Frequency Package 32117A–10/2010 Configuration Summary AT32UC3C0512C/ AT32UC3C0256C/ AT32UC3C0128C/ AT32UC3C064C 4 LQFP144 AT32UC3C AT32UC3C1512C/ AT32UC3C2512C/ AT32UC3C1256C/ AT32UC3C2256C/ AT32UC3C1128C/ AT32UC3C2128C/ AT32UC3C164C AT32UC3C264C MHz TQFP100 TQFP64/QFN64 7 ...
Page 8
Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in Figure 3-1. QFN64/TQFP64 Pinout Note: 32117A–10/2010 on QFN packages, the exposed pad is unconnected. AT32UC3C Table 3-1 on page 10. 8 ...
Page 9
Figure 3-2. TQFP100 Pinout 32117A–10/2010 AT32UC3C 9 ...
Page 10
Figure 3-3. LQFP144 Pinout 3.2 Peripheral Multiplexing on I/O lines 3.2.1 Multiplexed signals Each GPIO line can be assigned to one of the peripheral functions.The following table describes the peripheral signals multiplexed to the GPIO lines. Table 3-1. GPIO Controller ...
Page 11
Table 3-1. GPIO Controller Function Multiplexing x1/ x1/ x1/ x1/ x1/ x1/ x1/ x1/ ...
Page 12
Table 3-1. GPIO Controller Function Multiplexing x1/ x1/ x1/x2 45 x1/x2 46 x1/x2 47 x1/x2 48 x1/ 140 141 x1 99 143 x1 100 144 ...
Page 13
Table 3-1. GPIO Controller Function Multiplexing 17 x1/x2 18 x1/x2 19 x1/x2 20 x1/x2 57 x1/ x1/ x1/ x2/ x1/ x1/x2 63 x1/x2 64 x1/x2 65 x2/x4 66 x1/x2 67 ...
Page 14
Table 3-1. GPIO Controller Function Multiplexing x1/x2 82 x1/x2 83 x1/ x1/ x1/ x1/ x1/ ...
Page 15
Table 3-1. GPIO Controller Function Multiplexing 98 x1/x2 99 x1/x2 100 x1/x2 101 x1/x2 102 x1/x2 105 x1/x2 73 106 x1/ 107 x1/ 108 x1/ 109 x2/ 110 x1/x2 111 x1/x2 112 ...
Page 16
Table 3-1. GPIO Controller Function Multiplexing 124 x1/x2 125 x1/x2 126 x1/x2 127 x1/x2 128 x1/x2 129 x1/ 130 x1/x2 89 131 x1/x2 90 132 x1/x2 91 133 x1/x2 134 x1/x2 135 x1/ 136 x1/x2 59 ...
Page 17
Table 3-2. Function 3.2.3 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the System Control Interface (SCIF). Please refer to the SCIF ...
Page 18
OCD AXS register. For details, see the AVR32UC Techni- cal Reference Manual. Table 3-5. Pin EVTI_N MDO[5] MDO[4] MDO[3] MDO[2] MDO[1] MDO[0] EVTO_N MCKO MSEO[1] MSEO[0] 3.2.6 Other Functions The functions listed in pin ...
Page 19
Table 3-7. Signal Description List Signal Name Function VDDIN_5 1.8V Voltage Regulator Input VDDIN_33 USB I/O power supply VDDCORE 1.8V Voltage Regulator Output GNDIO I/O Ground GNDANA Analog Ground GNDCORE Ground of the core GNDPLL Ground of the PLLs AC0AN1/AC0AN0 ...
Page 20
Table 3-7. Signal Description List Signal Name Function MCKO Trace Data Output Clock MDO[5:0] Trace Data Output MSEO[1:0] Trace Frame Control EVTI_N Event In EVTO_N Event Out DATA aWire data DATAOUT aWire data output for 2-pin mode RXLINE[1:0] CAN channel ...
Page 21
Table 3-7. Signal Description List Signal Name Function SDCKE SDRAM Clock Enable SDCS SDRAM Chip Select SDWE SDRAM Write Enable EXTINT[8:1] External Interrupt Pins NMI_N = EXTINT[0] Non-Maskable Interrupt Pin General Purpose Input/Output - GPIOA, GPIOB, GPIOC, GPIOD PA[29:19] - ...
Page 22
Table 3-7. Signal Description List Signal Name Function RX_CLK Receive Clock RX_DV Receive Data Valid RX_ER Receive Coding Error SPEED Speed TXD[3:0] Transmit Data TX_CLK Transmit Clock or Reference Clock TX_EN Transmit Enable TX_ER Transmit Coding Error WOL Wake-On-LAN PAD_EVT[15:0] ...
Page 23
Table 3-7. Signal Description List Signal Name Function NPCS[3:0] SPI Peripheral Chip Select SCK Clock A0 Channel 0 Line A A1 Channel 1 Line A A2 Channel 2 Line A B0 Channel 0 Line B B1 Channel 1 Line B ...
Page 24
Table 3-7. Signal Description List Signal Name Function DP USB Device Port Data + VBUS USB VBUS Monitor and OTG Negociation ID ID Pin of the USB Bus VBOF USB VBUS On/off: bus power control port 3.4 I/O Line Considerations ...
Page 25
Processor and Architecture Rev: 2.1.2.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is pre- sented. For further details, see ...
Page 26
Load and store instructions have several different formats in order to reduce code size and speed up execution. The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack ...
Page 27
Figure 4-1. Instruction memory controller 4.3.1 Pipeline Overview AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc- tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) ...
Page 28
Figure 4-2. 4.3.2 AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar- geted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt ...
Page 29
Unaligned Reference Handling AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an address exception. Doubleword-sized accesses with word-aligned pointers will automatically ...
Page 30
Programming Model 4.4.1 Register File Configuration The AVR32UC register file is shown below. Figure 4-3. Application Bit 31 Bit SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC ...
Page 31
Figure 4-5. Bit 4.4.3 Processor States 4.4.3.1 Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 4-2. Priority N/A N/A Mode changes can ...
Page 32
Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 4.4.3.3 Secure State The AVR32 can be set in a secure state, that allows a part of the code ...
Page 33
Table 4-3. Reg # 33- ...
Page 34
Table 4-3. Reg # 100 101 102 103 104 105 106 107 108 109 110 111 112-191 192-255 4.5 Exceptions and Interrupts In the AVR32 architecture, events are used as ...
Page 35
EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception code segments ...
Page 36
Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes. The scall mechanism ...
Page 37
An instruction B is younger than an instruction was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in the exceptions are unused in AVR32UC since ...
Page 38
Table 4-4. Priority and Handler Addresses for Events Priority Handler Address 1 0x80000000 2 Provided by OCD system 3 EVBA+0x00 4 EVBA+0x04 5 EVBA+0x08 6 EVBA+0x0C 7 EVBA+0x10 8 Autovectored 9 Autovectored 10 Autovectored 11 Autovectored 12 EVBA+0x14 13 EVBA+0x50 ...
Page 39
Memories 5.1 Embedded Memories • Internal High-Speed Flash (See – 512 Kbytes – 256 Kbytes – 128 Kbytes – 64 Kbytes • Internal High-Speed SRAM, Single-cycle access at full speed (See – 64 Kbytes – 32 Kbytes – 16 ...
Page 40
Physical Memory Map The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. Note that AVR32UC CPU uses unsegmented translation, as described ...
Page 41
... Table 5-2. Part Number AT32UC3C0512C AT32UC3C1512C AT32UC3C2512C AT32UC3C0256C AT32UC3C1256C AT32UC3C2256C AT32UC3C0128C AT32UC3C1128C AT32UC3C2128C AT32UC3C064C AT32UC3C164C AT32UC3C264C 5.3 Peripheral Address Map Table 5-3. Peripheral Address Mapping Address 0xFFFD0000 0xFFFD1000 0xFFFD1400 0xFFFD1800 0xFFFD1C00 0xFFFD2000 0xFFFD2400 0xFFFD2800 0xFFFD2C00 0xFFFD3000 32117A–10/2010 Flash Memory Parameters ...
Page 42
Table 5-3. Peripheral Address Mapping 0xFFFE0000 0xFFFE1000 0xFFFE2000 0xFFFE2400 0xFFFE2800 0xFFFE2C00 0xFFFE3000 0xFFFF0000 0xFFFF0400 0xFFFF0800 0xFFFF0C00 0xFFFF1000 0xFFFF1400 0xFFFF1800 0xFFFF2000 0xFFFF2800 0xFFFF2C00 0xFFFF3000 0xFFFF3400 32117A–10/2010 HFLASHC Flash Controller - HFLASHC USBC USB 2.0 OTG Interface - USBC HMATRIX HSB Matrix ...
Page 43
Table 5-3. Peripheral Address Mapping 0xFFFF3800 0xFFFF3C00 0xFFFF4000 0xFFFF4400 0xFFFF4800 0xFFFF4C00 0xFFFF5000 0xFFFF5400 0xFFFF5800 0xFFFF5C00 0xFFFF6000 0xFFFF6400 0xFFFF6800 0xFFFF6C00 0xFFFF7000 5.4 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, ...
Page 44
The following GPIO registers are mapped on the local bus: Table 5-4. Port 32117A–10/2010 Local bus mapped GPIO registers Register Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) Output Driver Enable Register ...
Page 45
Table 5-4. Port 4 32117A–10/2010 Local bus mapped GPIO registers Register Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) AT32UC3C Local Bus Mode Address Access WRITE 0x4000_0640 Write-only SET 0x4000_0644 Write-only CLEAR 0x4000_0648 Write-only TOGGLE ...
Page 46
Supply and Startup Considerations 6.1 Supply Considerations 6.1.1 Power Supplies The AT32UC3C has several types of power supply pins: • VDDIO: Powers I/O lines and the flash. 2 Voltage ranges available 3.3V nominal. • VDDANA: Powers the ...
Page 47
Figure 6-1 on page 47 I/O lines and analog blocks will be powered by the same power (VDDIN_5 = VDDIO = VDDANA). Figure 6-1. 4.5-5.5V C IN2 VDDCORE C CORE2 GNDCORE 6.1.3.2 3.3V Single Supply Mode In 3.3V single supply ...
Page 48
Figure 6-2. 3.0-3.6V 6.1.4 Power-up Sequence 6.1.4.1 Maximum Rise Rate To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values described in Recommended order for power supplies is also described in this table. ...
Page 49
Startup Considerations This chapter summarizes the boot sequence of the AT32UC3C. The behavior after power-up is controlled by the Power Manager. For specific details, refer to the Power Manager chapter. 6.2.1 Starting of clocks At power-up, the BOD33 and ...
Page 50
Electrical Characteristics 7.1 Absolute Maximum Ratings* Operating temperature..................................... -40°C to +85°C Storage temperature...................................... -60°C to +150°C Voltage on any pin except DM/DP/VBUS with respect to ground ................... -0. Voltage on DM/DP with respect to ground.........-0.3V to +3.6V ...
Page 51
Table 7-2. Supply Rise Rates and Order Symbol Parameter V DC supply internal 3.3V regulator VDDIN_5 V DC supply internal 1.8V regulator VDDIN_33 V DC supply peripheral I/O VDDIO V DC supply analog part VDDANA 7.3 Maximum Clock Frequencies These ...
Page 52
I/Os are configured as inputs, with internal pull-up enabled. • Oscillators – OSC0/1 (crystal oscillator) stopped – OSC32K (32KHz crystal oscillator) stopped – PLL0 running – PLL1 stopped • Clocks – External clock on XIN0 as main clock source ...
Page 53
Figure 7-1. 7.4.1 Peripheral Power Consumption The values in conditions. • Operating conditions core supply – V – V – V – V – Internal 3.3V regulator is off. • 25°C A • I/Os are configured as inputs, ...
Page 54
PLL1 stopped • Clocks – External clock on XIN0 as main clock source. – CPU, HSB, and PB clocks undivided Consumption active is the added current consumption when the module clock is turned on and when the module is ...
Page 55
Notes: 7.5 I/O Pin Characteristics Table 7-6. Normal I/O Pin Characteristics Symbol Parameter R Pull-up resistance PULLUP R Pull-down resistance PULLDOWN V Input low-level voltage IL V Input high-level voltage IH V Output low-level voltage OL V Output high-level voltage ...
Page 56
Oscillator Characteristics 7.6.1 Oscillator (OSC0 and OSC1) Characteristics 7.6.1.1 Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN0 or XIN1. Table 7-7. Digital Clock Characteristics Symbol Parameter f ...
Page 57
Table 7-8. Crystal Oscillator Characteristics Symbol Parameter f Crystal oscillator frequency OUT C Crystal load capacitance L C Internal equivalent load capacitance i t Startup time STARTUP I Current consumption OSC Notes: 1. These values are guaranteed by design and ...
Page 58
RC Oscillator (RC120M) Characteristics Table 7-11. Internal 120MHz RC Oscillator Characteristics Symbol Parameter f Output frequency OUT I Current consumption RC120M t Startup time STARTUP Note: 1. These values are guaranteed by design and will be updated after ...
Page 59
Flash Characteristics Table 7-15 wait states. The FSW bit in the FLASHC FSR register controls the number of wait states used when accessing the flash memory. Table 7-15. Maximum Operating Frequency Flash Wait States 0 1 Table 7-16. Flash ...
Page 60
Analog Characteristics 7.8.1 1.8V Voltage Regulator Characteristics Table 7-18. 1.8V Voltage Regulator Electrical Characteristics Symbol Parameter V Input voltage range VDDIN_5 V Output voltage, calibrated value VDDCORE I DC output current OUT I Static current of regulator VREG Table ...
Page 61
Brown Out Detector (BOD18) Characteristics The values in Fuse register. Table 7-21. BODLEVEL Value Notes: 7.8.4 3.3V Brown Out Detector (BOD33) Characteristics The values in Table 7-23. ...
Page 62
Notes: 7.8.5 5V Brown Out Detector (BOD50) Characteristics The values in Table 7-25. BOD50.LEVEL Value Notes: 32117A–10/2010 1. These values are guaranteed by design and will be updated after characterization of current silicon. ...
Page 63
Analog to Digital Converter (ADC) Characteristics Table 7-27. Channel Conversion Time and ADC Clock Parameter Conditions 12-bit resolution mode - VDDANA = 5V 10-bit resolution mode - VDDANA = 5V 8-bit resolution mode - VDDANA = 5V ADC clock ...
Page 64
Table 7-29. Decoupling requirements Symbol Parameter ADCREFP-ADCREFN C ADCREFPN capacitance Table 7-30. ADC Inputs Parameter ADC input voltage range Input leakage current External source impedance Note: 1. These values are guaranteed by design and will be updated after characterization of ...
Page 65
Digital to Analog Converter (DAC) Characteristics Table 7-33. Channel Conversion Time and DAC Clock Parameter Startup time Throughput rate Note: 1. These values are guaranteed by design and will be updated after characterization of current silicon. Table 7-34. External ...
Page 66
Analog Comparator Characteristics Table 7-37. Analog Comparator Characteristics Parameter Positive input voltage range Negative input voltage range Offset Hysteresis Propagation delay Current consumption on VDDANA Start-up time Note: 1. These values are guaranteed by design and will be updated ...
Page 67
Timing Characteristics 7.9.1 Startup, Reset, and Wake-up Timing The startup, reset, and wake-up timings are calculated using the following formula CONST Where another clock source than RCSYS is selected as CPU clock the startup time of ...
Page 68
Mechanical Characteristics 8.1 Thermal Considerations 8.1.1 Thermal Data Table 8-1 Table 8-1. Symbol θ JA θ JC θ JA θ JC θ JA θ JC 8.1.2 Junction Temperature The average chip-junction temperature where: • ...
Page 69
Package Drawings Figure 8-1. QFN-64 package drawing Note: Table 8-2. Device and Package Maximum Weight TBD Table 8-3. Package Characteristics Moisture Sensitivity Level Table 8-4. Package Reference JEDEC Drawing Reference JESD97 Classification 32117A–10/2010 The exposed pad is not connected ...
Page 70
Figure 8-2. TQFP-64 package drawing Table 8-5. Device and Package Maximum Weight TBD Table 8-6. Package Characteristics Moisture Sensitivity Level Table 8-7. Package Reference JEDEC Drawing Reference JESD97 Classification 32117A–10/2010 mg Jdec J-STD0-20D - MSL 3 MS-026 E3 AT32UC3C 70 ...
Page 71
Figure 8-3. TQFP-100 package drawing Table 8-8. Device and Package Maximum Weight 500 Table 8-9. Package Characteristics Moisture Sensitivity Level Table 8-10. Package Reference JEDEC Drawing Reference JESD97 Classification 32117A–10/2010 mg Jdec J-STD0-20D - MSL 3 MS-026 E3 AT32UC3C 71 ...
Page 72
Figure 8-4. LQFP-144 package drawing Table 8-11. Device and Package Maximum Weight 1300 Table 8-12. Package Characteristics Moisture Sensitivity Level Table 8-13. Package Reference JEDEC Drawing Reference JESD97 Classification 32117A–10/2010 mg Jdec J-STD0-20D - MSL 3 MS-026 E3 AT32UC3C 72 ...
Page 73
Soldering Profile Table 8-14 Table 8-14. Profile Feature Average Ramp-up Rate (217°C to Peak) Preheat Temperature 175°C ±25°C Temperature Maintained Above 217°C Time within 5⋅C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25⋅C to Peak Temperature ...
Page 74
... Ordering Information Table 9-1. Device Ordering Code AT32UC3C0512C-ALUES AT32UC3C0512C AT32UC3C0512C-ALUT AT32UC3C0512C-ALUR AT32UC3C0256C-ALUT AT32UC3C0256C AT32UC3C0256C-ALUR AT32UC3C0128C-ALUT AT32UC3C0128C AT32UC3C0128C-ALUR AT32UC3C064C-ALUT AT32UC3C064C AT32UC3C064C-ALUR AT32UC3C1512C-AUES AT32UC3C1512C AT32UC3C1512C-AUT AT32UC3C1512C-AUR AT32UC3C1256C-AUT AT32UC3C1256C AT32UC3C1256C-AUR AT32UC3C1128C-AUT AT32UC3C1128C AT32UC3C1128C-AUR AT32UC3C164C-AUT AT32UC3C164C AT32UC3C164C-AUR 32UC3C2512C-A2UES 32UC3C2512C-A2UT 32UC3C2512C-A2UR AT32UC3C2512C 32UC3C2512C-Z2UES 32UC3C2512C-Z2UT 32UC3C2512C-Z2UR 32UC3C2256C-A2UT ...
Page 75
Errata 10.1 rev D 10.1.1 AST 1. AST wake signal is released one ast clock cycle after the busy register is cleared After writing to the Status Clear Register (SCR) the wake signal is released one AST clock cycle ...
Page 76
...
Page 77
AT32UC3C 77 ...
Page 78
Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 11.1 Rev. A – 10/10 1 32117A–10/2010 Initial revision ...
Page 79
Description ............................................................................................... 3 2 Overview ................................................................................................... 5 3 Package and Pinout ................................................................................. 8 4 Processor and Architecture .................................................................. 25 5 Memories ................................................................................................ 39 6 Supply and Startup Considerations ..................................................... 46 7 Electrical Characteristics ...................................................................... 50 8 Mechanical Characteristics ................................................................... ...
Page 80
Ordering Information ............................................................................. 74 10 Errata ....................................................................................................... 75 11 Datasheet Revision History .................................................................. 78 32117A–10/2010 8.1 Thermal Considerations ..................................................................................68 8.2 Package Drawings ...........................................................................................69 8.3 Soldering Profile ..............................................................................................73 10.1 rev D ................................................................................................................75 11.1 Rev. A – 10/10 .................................................................................................78 AT32UC3C 80 ...
Page 81
... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...