ATMEGA64L-8AUR Atmel, ATMEGA64L-8AUR Datasheet - Page 175
ATMEGA64L-8AUR
Manufacturer Part Number
ATMEGA64L-8AUR
Description
IC MCU AVR 64K 8MHZ 3V 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA64L-8AUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Frame Formats
2490Q–AVR–06/10
Figure 81. Synchronous Mode XCK Timing
The UCPOLn bit UCRSnC selects which XCK clock edge is used for data sampling and which is
used for data change. As
rising XCK edge and sampled at falling XCK edge. If UCPOLn is set, the data will be changed at
falling XCK edge and sampled at rising XCK edge.
A serial frame is defined to be one character of data bits with synchronization bits (start and stop
bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of
the following as valid frame formats:
•
•
•
•
A frame starts with the start bit followed by the least significant data bit. Then the next data bits,
up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit
is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can
be directly followed by a new frame, or the communication line can be set to an idle (high) state.
Figure 82
optional.
Figure 82. Frame Formats
The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in
UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing
St
(n)
P
Sp
IDLE
1 start bit
5, 6, 7, 8, or 9 data bits
no, even or odd parity bit
1 or 2 stop bits
UCPOLn = 1
UCPOLn = 0
Start bit, always low.
Data bits (0 to 8).
Parity bit. Can be odd or even.
Stop bit, always high.
No transfers on the communication line (RxD or TxD). An IDLE line must be
high.
illustrates the possible combinations of the frame formats. Bits inside brackets are
(IDLE)
RxD / TxD
RxD / TxD
St
XCK
XCK
0
Figure 81
1
2
shows, when UCPOLn is zero the data will be changed at
3
4
FRAME
[5]
[6]
[7]
[8]
[P]
Sample
Sample
Sp1 [Sp2]
ATmega64(L)
(St / IDLE)
175
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