ATMEGA128A-MNR Atmel, ATMEGA128A-MNR Datasheet - Page 14

• Manufacturer Part Number: ATMEGA128A-MNR
• Description: IC MCU AVR 128K FLASH 64VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-MNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Core: AVR8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.6.1
6.6.2
6.7
8151H–AVR–02/11
Instruction Execution Timing
SPH and SPL - Stack Pointer High and Low Register
RAMPZ - RAM Page Z Select Register
• Bits 7:1 – Reserved
These are reserved bits and will always read as zero. When writing to this address location,
write these bits to zero for compatibility with future devices.
• Bit 0 – RAMPZ0: Extended RAM Page Z-pointer
The RAMPZ Register is normally used to select which 64K RAM Page is accessed by the Z-
pointer. As the Atmel
this register is used only to select which page in the program memory is accessed when the
ELPM/SPM instruction is used. The different settings of the RAMPZ0 bit have the following
effects:
Note that LPM is not affected by the RAMPZ setting.
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 6-4
vard architecture and the fast-access Register file concept. This is the basic pipelining concept
to obtain up to 1MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
RAMPZ0 = 0:
RAMPZ0 = 1:
shows the parallel instruction fetches and instruction executions enabled by the Har-
SP15
R
7
–
0
R/W
R/W
SP7
15
7
0
0
Program memory address $0000 - $7FFF (lower 64Kbytes) is accessed by
ELPM/SPM
Program memory address $8000 - $FFFF (higher 64Kbytes) is accessed by
ELPM/SPM
®
AVR
R
6
–
0
SP14
R/W
R/W
SP6
14
6
0
0
®
ATmega128A does not support more than 64K of SRAM memory,
5
–
R
0
SP13
R/W
R/W
SP5
CPU
13
5
0
0
, directly generated from the selected clock source for the
R
4
–
0
SP12
R/W
R/W
SP4
12
4
0
0
R
3
–
0
SP11
R/W
R/W
SP3
11
3
0
0
R
2
–
0
SP10
SP2
R/W
R/W
10
2
0
0
R
1
–
0
ATmega128A
SP9
SP1
R/W
R/W
RAMPZ0
9
1
0
0
R/W
0
0
SP8
SP0
R/W
R/W
RAMPZ
8
0
0
0
SPH
SPL
14