ATMEGA64A-ANR Atmel, ATMEGA64A-ANR Datasheet - Page 162
ATMEGA64A-ANR
Manufacturer Part Number
ATMEGA64A-ANR
Description
IC MCU AVR 64K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA64A-MUR.pdf
(21 pages)
2.ATMEGA64A-AU.pdf
(392 pages)
3.ATMEGA64A-AU.pdf
(3 pages)
Specifications of ATMEGA64A-ANR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
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Price
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18. Output Compare Modulator (OCM1C2)
18.1
18.2
8160C–AVR–07/09
Overview
Description
The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier
frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit
Timer/Counter1 and the Output Compare Unit of the 8-bit Timer/Counter2. For more details
about these Timer/Counters see
on page 111
available in ATmega103 compatibility mode.
Figure 18-1. Output Compare Modulator, Block Diagram
When the modulator is enabled, the two Output Compare channels are modulated together as
shown in the block diagram
The Output Compare unit 1C and Output Compare unit 2 shares the PB7 port pin for output. The
outputs of the Output Compare units (OC1C and OC2) overrides the normal PORTB7 Register
when one of them is enabled (i.e., when COMnx1:0 is not equal to zero). When both OC1C and
OC2 are enabled at the same time, the modulator is automatically enabled.
The functional equivalent schematic of the modulator is shown on
includes part of the Timer/Counter units and the Port B pin 7 output driver circuit.Output Com-
pare Modulator, Schematic.
and
Timer/Counter1
Timer/Counter2
“8-bit Timer/Counter2 with PWM” on page
(Figure
“16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)”
18-1).
OC1C
OC2
146. Note that this feature is not
Figure
ATmega64A
OC2/PB7
OC1C/
Pin
. The schematic
162
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