ATMEGA32A-ANR Atmel, ATMEGA32A-ANR Datasheet - Page 20
![IC MCU AVR 32K FLASH 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA32A-ANR
Manufacturer Part Number
ATMEGA32A-ANR
Description
IC MCU AVR 32K FLASH 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA32A-MU.pdf
(353 pages)
Specifications of ATMEGA32A-ANR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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7.5
7.6
7.6.1
8155C–AVR–02/11
I/O Memory
Register Description
EEARH and EEARL – EEPROM Address Register
EEPROM data corruption can easily be avoided by following this design recommendation:
The I/O space definition of the Atmel
page
All ATmega32A I/Os and peripherals are placed in the I/O space. The I/O locations are
accessed by the IN and OUT instructions, transferring data between the 32 general purpose
working registers and the I/O space. I/O Registers within the address range $00 - $1F are
directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single
bits can be checked by using the SBIS and SBIC instructions. Refer to the Instruction Set sec-
tion for more details. When using the I/O specific commands IN and OUT, the I/O addresses $00
- $3F must be used. When addressing I/O Registers as data space using LD and ST instruc-
tions, $20 must be added to these addresses.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI
instructions will operate on all bits in the I/O Register, writing a one back into any flag read as
set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.
The I/O and Peripherals Control Registers are explained in later sections.
• Bits [15:10] – Reserved Bits
These bits are reserved bits in the ATmega32A and will always read as zero.
• Bits [9:0] – EEAR9:0: EEPROM Address
The EEPROM Address Registers
1024bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
1023. The initial value of EEAR is undefined. A proper value must be written before the
EEPROM may be accessed.
Bit
Read/Write
Initial Value
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This
can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the
internal BOD does not match the needed detection level, an external low V
tion circuit can be used. If a reset occurs while a write operation is in progress, the write
operation will be completed provided that the power supply voltage is sufficient.
335.
EEAR7
R/W
15
R
X
–
7
0
EEAR6
R/W
14
R
X
–
6
0
EEAR5
R/W
–
13
R
X
–
5
0
EEARH and EEARL – specify the EEPROM address in the
®
AVR
EEAR4
R/W
®
12
R
X
–
4
0
ATmega32A is shown in
EEAR3
R/W
11
R
X
–
3
0
EEAR2
R/W
10
R
X
–
2
0
EEAR9
EEAR1
R/W
R/W
X
“Register Summary” on
9
1
0
ATmega32A
EEAR8
EEAR0
CC
R/W
R/W
X
X
8
0
Reset Protec-
EEARH
EEARL
20
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