LPC1112FHN33/202,5 NXP Semiconductors, LPC1112FHN33/202,5 Datasheet - Page 12

• Manufacturer Part Number: LPC1112FHN33/202,5
• Description: IC MCU LV 32BIT 16K FLAS 32VQFN
• Manufacturer: NXP Semiconductors
• Series: LPC1100Lr

Specifications of LPC1112FHN33/202,5

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: LPC1112
• Core: ARM Cortex-M0
• Data Bus Width: 32 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, UART, SPI, SSP
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 42
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-5145

IRQVECTOR
IRQHandler PROC
ENDP
Writing interrupt handlers
Traditional approach
STMFD sp!,{r0-r4,r12,lr}
MOV r4,#0x80000000
LDR r0,[r4,#0]
SUB sp,sp,#4
CMP r0,#1
BLEQ C_int_handler
MOV r0,#0
STR r0,[r4,#4]
ADD sp,sp,#4
LDMFD sp!,{r0-r4,r12,lr}
SUBS pc,lr,#4
Exception table
Top-level handler
– Fetch instruction to branch
– Routine handles re-entrancy
LDR
PC, IRQHandler
.
.
ARM Cortex-M family
NVIC automatically handles
ISR can be written directly in C
Faster interrupt response
WFI, sleep on exit
– Saving corruptible registers
– Exception prioritization
– Exception nesting
– Pointer to C routine at vector
– ISR is a C function
– With less software effort
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