SST89V58RD2-33-C-NJE Microchip Technology, SST89V58RD2-33-C-NJE Datasheet - Page 31

• Manufacturer Part Number: SST89V58RD2-33-C-NJE
• Description: IC MCU 8BIT 40KB FLASH 44PLCC
• Manufacturer: Microchip Technology
• Series: FlashFlex®r

Specifications of SST89V58RD2-33-C-NJE

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 44-LCC (J-Lead)
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 36
• Eeprom Size: 8K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: SST89xxxRD
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FlashFlex MCU
SST89V54RD2/RD / SST89V58RD2/RD
Timer/Counter 2 Control Register (T2CON)
Timer/Counter 2 Mode Control (T2MOD)
©2007 Silicon Storage Technology, Inc.
Location
Location
C8H
C9H
Symbol
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
Symbol
X
-
T2OE
DCEN
TF2
7
7
X
EXF2
6
Function
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2
will not be set when either RCLK or TCLK = 1.
Timer 2 external flag set when either a capture or reload is caused by a negative
transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will
cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by
software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for
its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for
the receive clock.
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for
its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflow to be used for
the transmit clock.
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result
of a negative transition on T2EX if Timer 2 is not being used to clock the serial port.
EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
Start/stop control for Timer 2. A logic 1 starts the timer.
Timer or counter select (Timer 2)
0: Internal timer (OSC/6 in 6 clock mode, OSC/12 in 12 clock mode)
1: External event counter (falling edge triggered)
Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if
EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or
negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1,
this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
6
Function
Don’t Care
Not implemented, reserved for future use.
Note: User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate.
Timer 2 Output Enable bit.
Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down
counter.
-
RCLK
5
5
-
TCLK
4
4
-
31
EXEN2
3
3
-
TR2
2
2
-
C/T2#
T2OE
1
1
CP/RL2#
DCEN
0
0
S71255-10-000
Reset Value
Reset Value
Data Sheet
xxxxxx00b
00H
12/07