SST89V58RD2-33-C-NJE Microchip Technology, SST89V58RD2-33-C-NJE Datasheet - Page 24

• Manufacturer Part Number: SST89V58RD2-33-C-NJE
• Description: IC MCU 8BIT 40KB FLASH 44PLCC
• Manufacturer: Microchip Technology
• Series: FlashFlex®r

Specifications of SST89V58RD2-33-C-NJE

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 44-LCC (J-Lead)
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 36
• Eeprom Size: 8K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: SST89xxxRD
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Data Sheet
Auxiliary Register (AUXR)
Auxiliary Register 1 (AUXR1)
Watchdog Timer Control Register (WDTC)
©2007 Silicon Storage Technology, Inc.
Location
Location
Location
C0H
8EH
A2H
Symbol
EXTRAM
AO
Symbol
GF2
DPS
Symbol
WDOUT
WDRE
WDTS
WDT
SWDT
7
7
7
-
-
-
6
Function
Internal/External RAM access
0: Internal Expanded RAM access within range of 00H to 2FFH using MOVX @Ri /
@DPTR. Beyond 300H, the MCU always accesses external data memory.
For details, refer to Section 3.4, “Expanded Data RAM Addressing” .
1: External data memory access.
Disable/Enable ALE
0: ALE is emitted at a constant rate of 1/3 the oscillator frequency in 6 clock mode, 1/6 f
12 clock mode.
1: ALE is active only during a MOVX or MOVC instruction.
6
Function
General purpose user-defined flag.
DPTR registers select bit.
0: DPTR0 is selected.
1: DPTR1 is selected.
6
Function
Watchdog output enable.
0: Watchdog reset will not be exported on Reset pin.
1: Watchdog reset if enabled by WDRE, will assert Reset pin for 32 clocks.
Watchdog timer reset enable.
0: Disable watchdog timer reset.
1: Enable watchdog timer reset.
Watchdog timer reset flag.
0: External hardware reset or power-on reset clears the flag.
1: Hardware sets the flag on watchdog overflow.
Watchdog timer refresh.
0: Hardware resets the bit when refresh is done.
1: Software sets the bit to force a watchdog timer refresh.
Start watchdog timer.
0: Stop WDT.
1: Start WDT.
-
-
-
Flag can also be cleared by writing a 1.
Flag survives if chip reset happened because of watchdog timer overflow.
5
5
5
-
-
-
WDOUT
4
4
4
-
-
24
WDRE
GF2
3
3
3
SST89V54RD2/RD / SST89V58RD2/RD
-
WDTS
2
2
0
2
-
EXTRAM
WDT
1
1
1
-
SWDT
DPS
FlashFlex MCU
AO
0
0
0
S71255-10-000
Reset Value
Reset Value
Reset Value
xxx00000b
xxxx00x0b
xxxxxx00b
OSC
12/07
in