ATTINY88-MMUR Atmel, ATTINY88-MMUR Datasheet - Page 23

• Manufacturer Part Number: ATTINY88-MMUR
• Description: MCU AVR 8KB FLASH 12MHZ 32QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY88-MMUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9. Datasheet Revision History
9.1
9.2
9.3
9.4
8008F–AVR–06/10
Rev. 8008F - 06/10
Rev. 8008E - 05/10
Rev. 8008D - 03/10
Rev. 8008C - 03/09
Please note that page references in this section refer to the current revision of this document.
1. Updated notes 1 and 10 in table in
2. Updated package drawing in
3. Updated bit syntax throughout the datasheet, e.g. from CS02:0 to CS0[2:0].
1.
2.
1. Separated Typical Characteristic plots, added
2. Updated:
3. Added:
1. Updated sections:
Section 4. “Register Summary” on page
Section 7.1 “28M1” on page 16
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– UFBGA package (32CC1) in,
– Addresses in all Register Desc. tables, with cross-references to Register Summary
– Tape and reel in
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Section 1.1 “Pin Descriptions” on page
and ‘high sink’.
Table 6-3 on page 28
Section 6.4 “128 kHz Internal Oscillator” on page 28
Section 8.4 “Watchdog Timer” on page
Section 21.2 “DC Characteristics” on page
Section 6. “Ordering Information” on page
Information” on page 16
“Features” on page 1
“Reset and Interrupt Handling” on page 13
“EECR – EEPROM Control Register” on page 22
“Features” on page 127
“Bit Rate Generator Unit” on page 133
“TWBR – TWI Bit Rate Register” on page 154
“TWHSR – TWI High Speed Register” on page 157
“Analog Comparator” on page 158
“Overview” on page 161
“Operation” on page 162
“Starting a Conversion” on page 163
Section 6. “Ordering Information” on page 14
adjusted, to fix TBD.
Section 7.4 “32CC1” on page
updated with correct package drawing.
“Features” on page
Section 21.2 “DC Characteristics” on page
8, added SPH at address 0x3E.
3, Port D, adjusted texts ‘sink and source’
43, updated.
14, and
204, updated TBD in notes 5 and 8.
Section 22.2 “ATtiny88” on page
1,
Section 7. “Packaging
“Pin Configurations” on page
adjusted, to fix TBD.
19.
204.
247.
2,
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