ATTINY861V-10SUR Atmel, ATTINY861V-10SUR Datasheet - Page 93
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ATTINY861V-10SUR
Manufacturer Part Number
ATTINY861V-10SUR
Description
IC MCU AVR 8K FLASH 10MHZ 20SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY861V-10SUR
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
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12.3.1.1
12.3.1.2
12.4
2588E–AVR–08/10
Counter Unit
Prescaler Reset
Prescaler Initialization for Asynchronous Mode
Setting the PSR1 bit in TCCR1B register resets the prescaler. It is possible to use the Prescaler
Reset for synchronizing the Timer/Counter to program execution.
To change Timer/Counter1 to the asynchronous mode follow the procedure below:
The main part of the Timer/Counter1 is the programmable bi-directional counter unit.
4
Figure 12-4. Counter Unit Block Diagram
Signal description (internal signals):
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
asynchronous PLL clock using the Clock Select bits (CS13:0) and the PCK Enable bit (PCKE).
When no clock source is selected (CS13:0 = 0) the timer is stopped. However, the TCNT1 value
can be accessed by the CPU, regardless of whether clk
rides (has priority over) all counter clear or count operations.
The counting sequence of the Timer/Counter1 is determined by bits WGM11:10, PWM1A and
PWM1B, located in the Timer/Counter1 Control Registers (TCCR1A, TCCR1C and TCCR1D).
For more details about advanced counting sequences and waveform generation, see
Operation” on page
of operation and can be used for generating a CPU interrupt.
shows a block diagram of the counter and its surroundings.
1. Enable PLL.
2. Wait 100 µs for PLL to stabilize.
3. Poll the PLOCK bit until it is set.
4. Set the PCKE bit in the PLLCSR register which enables the asynchronous mode.
count
direction
clear
clk
top
bottom
Tn
DATA BUS
TCNT1
99. The Timer/Counter Overflow Flag (TOV1) is set according to the mode
T1
). The timer clock is generated from an synchronous system clock or an
TCNT1 increment or decrement enable.
Select between increment and decrement.
Clear TCNT1 (set all bits to zero).
Timer/Counter clock, referred to as clk
Signalize that TCNT1 has reached maximum value.
Signalize that TCNT1 has reached minimum value (zero).
direction
count
clk
clear
T1
bottom
Control Logic
T1
top
is present or not. A CPU write over-
TOV1
T1
PCKE
PCK
CK
Timer/Counter1 Count Enable
( From Prescaler )
in the following.
Figure 12-
“Modes of
93
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