ATTINY861V-10SUR Atmel, ATTINY861V-10SUR Datasheet - Page 175
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ATTINY861V-10SUR
Manufacturer Part Number
ATTINY861V-10SUR
Description
IC MCU AVR 8K FLASH 10MHZ 20SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY861V-10SUR
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
ATTINY861V-10SUR
Manufacturer:
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Quantity:
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18.6.2
2588E–AVR–08/10
Serial Programming Instruction set
Table 18-10. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
The instruction set is described in
Symbol
t
t
t
t
5. A: The EEPROM array is programmed one byte at a time by supplying the address and
6. Any memory location can be verified by using the Read instruction which returns the
7. At the end of the programming session, RESET can be set high to commence normal
8. Power-off sequence (if needed):
WD_FLASH
WD_EEPROM
WD_ERASE
WD_FUSE
interface before the Flash write operation completes can result in incorrect
programming.
data together with the appropriate Write instruction. An EEPROM memory location is
first automatically erased before new data is written. If polling (RDY/BSY) is not used,
the user must wait at least t
In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded
one byte at a time by supplying the 2 LSB of the address and data together with the
Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by
loading the Write EEPROM Memory Page Instruction with the 6 MSB of the address.
When using EEPROM page access only byte locations loaded with the Load EEPROM
Memory Page instruction is altered. The remaining locations remain unchanged. If poll-
ing (RDY/BSY) is not used, the used must wait at least t
next page (See
be programmed.
content at the selected address at serial output MISO.
operation.
Set RESET to “1”.
Turn V
CC
power off.
Table
18-8). In a chip erased device, no 0xFF in the data file(s) need to
WD_EEPROM
Table 18-11 on page 176
before issuing the next byte. (See
Minimum Wait Delay
and
WD_EEPROM
4.5 ms
4.0 ms
9.0 ms
4.5 ms
Figure 18-2 on page
before issuing the
Table
18-10.)
177.
175
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