ATTINY13A-SNR Atmel, ATTINY13A-SNR Datasheet - Page 38

• Manufacturer Part Number: ATTINY13A-SNR
• Description: IC MCU AVR 1KB FLASH 20MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY13A-SNR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (512 x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 8-SOIC (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

8.2.4
8.3
8.3.1
8.4
38
Internal Voltage Reference
Watchdog Timer
ATtiny13A
Watchdog Reset
Voltage Reference Enable Signals and Start-up Time
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period t
“Interrupts” on page 45
Figure 8-6.
ATtiny13A features an internal bandgap reference. This reference is used for Brown-out Detec-
tion, and it can be used as an input to the Analog Comparator or the ADC.
The voltage reference has a start-up time that may influence the way it should be used. The
start-up time is given in
reference is not always turned on. The reference is on during the following situations:
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
ATtiny13A has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a
separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a system reset when the
counter reaches a given time-out value. In normal operation mode, it is required that the system
uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out
• When the BOD is enabled (by programming the BODLEVEL[1:0] fuse).
• When the bandgap reference is connected to the Analog Comparator (by setting the ACBG
• When the ADC is enabled.
bit in ACSR).
CC
Watchdog Reset During Operation
for details on operation of the Watchdog Timer.
“System and Reset Characteristics” on page
CK
120. To save power, the
8126E–AVR–07/10
TOUT
. Refer to