NUC120RD1BN Nuvoton Technology Corporation of America, NUC120RD1BN Datasheet - Page 532
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NUC120RD1BN
Manufacturer Part Number
NUC120RD1BN
Description
IC MCU 32BIT 64KB FLASH 64LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™r
Specifications of NUC120RD1BN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
Number Of I /o
45
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NUC120RD1BN
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
- NUC100LC1BN PDF datasheet
- NUC100LC1BN_PRODUCT_CHANGE PDF datasheet #2
- NUC120LC1BN PDF datasheet #3
- NUC120LC1BN PDF datasheet #4
- Current page: 532 of 600
- Download datasheet (6Mb)
PDMA Global Control and Status Register (PDMA_GCRCSR)
Register
PDMA_GCRCSR
Bits
[31:17]
[16]
[15]
[14]
[13]
[12]
[11
[10
CLK7_EN
31
23
15
7
NuMicro™ NUC100 Series Technical Reference Manual
Descriptions
Reserved
CLK8_EN
CLK7_EN
CLK6_EN
CLK5_EN
CLK4_EN
CLK3_EN
CLK2_EN
CLK6_EN
Offset
PDMA_BA_GCR+0x00 R/W
30
22
14
6
CLK5_EN
Reserved
PDMA Controller Channel 8 Clock Enable Control (Medium Density Only)
0 = Disable
1 = Enable
PDMA Controller Channel 7 Clock Enable Control (Medium Density Only)
0 = Disable
1 = Enable
PDMA Controller Channel 6 Clock Enable Control (Medium Density Only)
0 = Disable
1 = Enable
PDMA Controller Channel 5 Clock Enable Control (Medium Density Only)
0 = Disable
1 = Enable
PDMA Controller Channel 4 Clock Enable Control (Medium Density Only)
0 = Disable
1 = Enable
PDMA Controller Channel 3 Clock Enable Control (Medium Density Only)
0 = Disable
1 = Enable
PDMA Controller Channel 2 Clock Enable Control (Medium Density Only)
0 = Disable
1 = Enable
29
21
13
5
R/W
CLK4_EN
Reserved
Description
PDMA Global Control and Status Register
28
20
12
4
- 532 -
Reserved
Reserved
CLK3_EN
27
19
11
3
Publication Release Date: Dec. 22, 2010
CLK2_EN
26
18
10
2
CLK1_EN
25
17
9
1
Revision V1.06
Reset Value
0x0000_0000
CLK8_EN
CLK0_EN
24
16
8
0
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