NUC120RD1BN Nuvoton Technology Corporation of America, NUC120RD1BN Datasheet - Page 24
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NUC120RD1BN
Manufacturer Part Number
NUC120RD1BN
Description
IC MCU 32BIT 64KB FLASH 64LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™r
Specifications of NUC120RD1BN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
Number Of I /o
45
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NUC120RD1BN
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
- NUC100LC1BN PDF datasheet
- NUC100LC1BN_PRODUCT_CHANGE PDF datasheet #2
- NUC120LC1BN PDF datasheet #3
- NUC120LC1BN PDF datasheet #4
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- Download datasheet (6Mb)
• I
• I
• PS2 Device Controller
• CAN 2.0
• EBI (External bus interface) support (Low Density 64-pin Package Only)
• ADC
2
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C
S
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Up to two sets of I
Master/Slave up to 1Mbit/s
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
Programmable clocks allow versatile rate control
Support multiple address recognition (four slave address with mask option)
Interface with external audio CODEC
Operate as either master or slave mode
Capable of handling 8, 16, 24 and 32 bit word sizes
Mono and stereo audio data supported
I
Two 8 word FIFO data buffers are provided, one for transmit and one for receive
Generates interrupt requests when buffer levels cross a programmable boundary
Support two DMA requests, one for transmit and one for receive
Host communication inhibit and request to send detection
Reception frame error detection
Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention
Double buffer for data reception
S/W override bus
CAN 2.0B protocol compatible device
Support 11-bit identifier as well as 29-bit identifier
Bit rates up to 1Mbits/s
NRZ bit Coding/ Encoding
Error Detection & Status Report
Bit Timing Synchronization
Acceptance filter extension
Sleep mode wake up
Accessible space: 64KB in 8-bit mode or 128KB in 16-bit mode
Support 8bit/16bit data width
Support byte write in 16bit data width mode
12-bit SAR ADC with 600K SPS
Up to 8-ch single-end input or 4-ch differential input
Single scan/single cycle scan/continuous scan
Each channel with individual result register
Scan on enabled channels
NuMicro™ NUC100 Series Technical Reference Manual
2
S and MSB justified data format supported
Bit error, Form error, Stuffing error, 15-bit CRC detection, and Acknowledge
error Interrupt
Each CAN-bus error and Transmission/Receive Done
2
C device
- 24 -
Publication Release Date: Dec. 22, 2010
Revision V1.06
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