M0516ZAN Nuvoton Technology Corporation of America, M0516ZAN Datasheet - Page 260

IC MCU 32BIT 64KB FLASH 33QFN

M0516ZAN

Manufacturer Part Number
M0516ZAN
Description
IC MCU 32BIT 64KB FLASH 33QFN
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro M051™r
Datasheets

Specifications of M0516ZAN

Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 5x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
33-WFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M0516ZAN
Manufacturer:
Nuvoton
Quantity:
200
Part Number:
M0516ZAN
Manufacturer:
NUVOTON
Quantity:
20 000
Timer Control Register (TCSR)
Register
TCSR0
TCSR1
TCSR2
TCSR3
Bits
[31]
[30]
[29]
[28:27]
Reserved
31
23
15
7
NuMicro M051
Offset
TMR_BA01+000
TMR_BA01+020
TMR_BA23+000
TMR_BA23+020
Descriptions
Reserved
CEN
IE
MODE
CEN
30
22
14
6
R/W
R/W
R/W
R/W
R/W
Reserved
Timer Enable Bit
0 = Stops/Suspends counting
1 = Starts counting
Note1: In stop status, and then set CEN to 1 will enables the 24-bit timer keeps up
counting from the last stop counting value.
Note2: This bit is auto-cleared by hardware in one-shot mode (MODE [28:27] =00)
when the associated timer interrupt is generated (IE [29] =1).
Interrupt Enable Bit
0 = Disable timer Interrupt
1 = Enable timer Interrupt
If timer interrupt is enabled, the timer asserts its interrupt signal when the associated
timer is equal to TCMPR.
Timer Operating Mode
29
21
13
IE
5
Description
Timer0 Control and Status Register
Timer1 Control and Status Register
Timer2 Control and Status Register
Timer3 Control and Status Register
Series Technical Reference Manual
Reserved
28
20
12
PRESCALE[7:0]
4
MODE[1:0]
- 260 -
Reserved
27
19
11
3
Publication Release Date: Sep 14, 2010
CRST
26
18
10
2
CACT
25
17
9
1
Revision V1.2
Reset Value
0x0000_0005
0x0000_0005
0x0000_0005
0x0000_0005
Reserved
TDR_EN
24
16
8
0

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