XC3S1600E-4FG484I Xilinx Inc, XC3S1600E-4FG484I Datasheet - Page 14

• Manufacturer Part Number: XC3S1600E-4FG484I
• Description: IC FPGA SPARTAN 3E 484FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S1600E-4FG484I

• Number Of Logic Elements/cells: 33192
• Number Of Labs/clbs: 3688
• Total Ram Bits: 663552
• Number Of I /o: 376
• Number Of Gates: 1600000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-BBGA
• Dc: 1121
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Functional Description
Table 5: Storage Element Options (Continued)
Double-Data-Rate Transmission
Double-Data-Rate (DDR) transmission describes the tech-
nique of synchronizing signals to both the rising and falling
edges of the clock signal. Spartan-3E devices use register
pairs in all three IOB paths to perform DDR operations.
The pair of storage elements on the IOB’s Output path
(OFF1 and OFF2), used as registers, combine with a spe-
cial multiplexer to form a DDR D-type flip-flop (ODDR2).
This primitive permits DDR transmission where output data
bits are synchronized to both the rising and falling edges of
a clock. DDR operation requires two clock signals (usually
50% duty cycle), one the inverted form of the other. These
signals trigger the two registers in alternating fashion, as
shown in
erates the two clock signals by mirroring an incoming signal,
and then shifting it 180 degrees. This approach ensures
minimal skew between the two signals. Alternatively, the
inverter inside the IOB can be used to invert the clock sig-
nal, thus only using one clock line and both rising and falling
edges of that clock line as the two clocks for the DDR
flip-flops.
14
SRHIGH/SRLOW
INIT1/INIT0
Option Switch
Figure
7. The Digital Clock Manager (DCM) gen-
180˚ 0˚
DCM
Determines whether SR acts as a Set, which
forces the storage element to a logic "1"
(SRHIGH) or a Reset, which forces a logic "0"
(SRLOW)
When Global Set/Reset (GSR) is asserted or
after configuration this option specifies the
initial state of the storage element, either set
(INIT1) or reset (INIT0). By default, choosing
SRLOW also selects INIT0; choosing SRHIGH
also selects INIT1.
Figure 7: Two Methods for Clocking the DDR Register
D1
D2
CLK1
CLK2
Q1
Q2
Function
DDR MUX
FDDR
www.xilinx.com
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The storage-element pair on the Three-State path (TFF1
and TFF2) also can be combined with a local multiplexer to
form a DDR primitive. This permits synchronizing the output
enable to both the rising and falling edges of a clock. This
DDR operation is realized in the same way as for the output
path.
The storage-element pair on the input path (IFF1 and IFF2)
allows an I/O to receive a DDR signal. An incoming DDR
clock signal triggers one register, and the inverted clock sig-
nal triggers the other register. The registers take turns cap-
turing bits of the incoming DDR data signal. The primitive to
allow this functionality is called IDDR2.
Aside from high bandwidth data transfers, DDR outputs also
can be used to reproduce, or mirror, a clock signal on the
output. This approach is used to transmit clock and data sig-
nals together (source synchronously). A similar approach is
used to reproduce a clock signal at multiple outputs. The
advantage for both approaches is that skew across the out-
puts is minimal.
DCM
0˚
Independent for each storage element, except
when using ODDR2. In the latter case, the selection
for the upper element will apply to both elements.
Independent for each storage element, except
when using ODDR2, which uses two IOBs. In the
ODDR2 case, selecting INIT0 for one IOBs applies
to both elements within the IOB, although INIT1
could be selected for the elements in the other IOB.
D1
D2
CLK1
CLK2
Q1
Q2
Specificity
DDR MUX
DS312-2 (v3.8) August 26, 2009
FDDR
DS312-2_20_021105
Product Specification
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