XR17V258IV-F Exar Corporation, XR17V258IV-F Datasheet - Page 22

IC UART PCI BUS OCTAL 144LQFP

XR17V258IV-F

Manufacturer Part Number
XR17V258IV-F
Description
IC UART PCI BUS OCTAL 144LQFP
Manufacturer
Exar Corporation
Type
Octal UARTr
Datasheet

Specifications of XR17V258IV-F

Number Of Channels
8
Package / Case
144-LQFP
Features
*
Fifo's
64 Byte
Protocol
RS485
Voltage - Supply
3.3V, 5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Data Rate
8 Mbps
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current
4 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 45 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3 V to 3.6 V
No. Of Channels
8
Uart Features
Tx/Rx FIFO Counters
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
LQFP
No. Of Pins
144
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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XR17V258
66MHZ PCI BUS OCTAL UART WITH POWER MANAGEMENT SUPPORT
Timer Operation in Re-triggerable Mode:
In the re-triggerable mode, when the Timer is started, the Timer output will stay HIGH until it reaches half of the
terminal count N (= P clocks) and toggle LOW and stay LOW for a similar amount of time (Q clocks). The
above step will keep repeating until the Timer is stopped at which time the output will become HIGH (default
state). See
triggerable mode. The Timer must be programmed while it is stopped since the following operations are
blocked when the Timer is running:
Routing the Timer Output to MPIO[0] Pin:
MPIO[0] pin is by default (on power up or reset, for example) an input. However, whenever the Timer output is
routed to MPIO[0] pin,
Timer Interrupt
In the one-shot mode, the Timer will issue an interrupt upon timing out which is ’N’ clocks after the Timer is
started. In the re-triggerable mode, the Timer will keep issuing an interrupt every ’N’ clocks which is on every
rising edge of the Timer output. The Timer interrupt can be cleared by reading the TIMERCNTL register or
when a Timer Reset command is issued which brings the Timer back to its default settings. The TIMERCNTL
will read a value of 0x01 when the Timer interrupt is enabled and there is a pending interrupt. It reads a value
of 0x00 at all other times. Stopping the Timer does not clear the interrupt and neither does subsequent re-
starting.
F
IGURE
TIMER Output in
TIMER Output in
One-Shot Mode
Re-triggerable
Any write to TIMER MSB, LSB registers
Issue of any command other than ’Stop Timer’ and ’Reset Timer’ (’Start Timer’ is not allowed)
MPIO[0] will be automatically selected as an output
MPIO[0] will become HIGH (the default state of Timer output)
All MPIO control registers (MPIOLVL, MPIOSEL etc) lose control over MPIO[0] and get the control back
only when the Timer output is de-routed from MPIO[0].
7. T
Mode
Figure 7
IMER
O
UTPUT IN
. Also, after the Timer is started, re-starting the Timer does not have any effect in re-
COMMAND ISSUED
START TIMER
< 'N' Clocks
O
NE
After 'P'
clocks
-S
HOT AND
START TIMER COMMANDS ISSUED: LESS THAN 'N'
After 'Q'
CLOCKS BETWEEN SUCCESSIVE COMMANDS
clocks
R
After 'P'
clocks
E
-
TRIGGERABLE
After 'Q'
clocks
22
After 'P'
clocks
M
< 'N' Clocks
ODES
COMMAND ISSUED
After 'Q'
clocks
START TIMER
After 'P'
clocks
'N' Clocks
After 'Q'
clocks
After 'P'
clocks
COMMAND ISSUED
STOP TIMER
REV. 1.0.2

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