XRD9836ACG Exar Corporation, XRD9836ACG Datasheet - Page 23

no-image

XRD9836ACG

Manufacturer Part Number
XRD9836ACG
Description
IC 16B CCD/CIS SIG PROC 48TSSOP
Manufacturer
Exar Corporation
Datasheet

Specifications of XRD9836ACG

Package / Case
48-TSSOP (0.240", 6.10mm Width)
Number Of Bits
16
Number Of Channels
3
Power (watts)
500mW
Voltage - Supply, Analog
3 V ~ 3.6 V
Voltage - Supply, Digital
3 V ~ 3.6 V
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Contains lead / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XRD9836ACG
Manufacturer:
TOREX
Quantity:
10 000
Part Number:
XRD9836ACG-F
Manufacturer:
EXAR
Quantity:
432
Part Number:
XRD9836ACG-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
Company:
Part Number:
XRD9836ACG-F
Quantity:
514
Company:
Part Number:
XRD9836ACG-F
Quantity:
1 014
xr
xr
Control / Polarity
Register
CNTRL / POL
(01111)
default
The CNTRL / POL register is used to program various options including: input timing polarity control, dynamic low
power disable, power down for the chip, output enable, and reset. Reset will reset ALL registers including reset.
All the clock inputs (except the serial interface SCLK) can be programmed to be active high or active low. See the “Tim-
ing” section for more information. ADCpol, LCLMPpol, BSAMPpol, and VSAMPpol set the polarity of ADCLK, LCLMP,
BSAMP, and VSAMP respectively.
ADCpol - Sets the polarity of the ADCLK input. ADCpol = 0, ADCLK low during VSAMP. ADCpol = 0, ADCLK inverted
so that it is high during VSAMP.
LCLMPpol - Sets the polarity of the LCLMP input. LCLMPpol = 0, LCMLP is active high during clamping operation and
odd pixel determined from falling edge.
BSAMPpol - Sets the polarity of the BSAMP input. BSAMPpol = 0, BSAMP is active high. The CCD black level is sam-
ple by the falling edge. BSAMPpol = 1, BSAMP is active low. The CCD black level is sample by the rising edge.
VSAMPpol - Sets the polarity of the VSAMP input. VSAMPpol = 0, VSAMP is active high. The CCD video level is sam-
ple by the falling edge. VSAMPpol = 1, VSAMP is active low. The CCD video level is sample by the rising edge.
DLP DISABLE (ADC Dynamic Low Power Disable)
PWRDWN - Puts the XRD9836 into power down state. PWRDWN = 0, normal operation. PWRDWN = 1, low power
state.
OEB - Enables the ADCDO bus. OEB = 0, data valid on ADCDO bus. OEB = 1, ADCDO bus high impedance.
RESET - Will reset the XRD9836 to default (power up) conditions. RESET = 0, normal operation. RESET = 1, all inter-
nal registers set to default values and clears itself after ~ 10ns.
D9
D8
ADC
POL
D7
0
LCLMP
POL
D6
0
23
BSAMP
POL
D5
0
VSAMP
POL
D4
0
DISABLE
DLP
D3
0
16-BIT PIXEL GAIN AFE
PWRDWN
D2
0
OEB
D1
0
XRD9836
REV. 1.0.0
RESET
D0
0

Related parts for XRD9836ACG