XR18W750IL48-F Exar Corporation, XR18W750IL48-F Datasheet - Page 26

• Manufacturer Part Number: XR18W750IL48-F
• Description: IC WIRELESS UART CTRLR 48QFN
• Manufacturer: Exar Corporation

Specifications of XR18W750IL48-F

• Package / Case: 48-VFQFN Exposed Pad
• Function: Controller
• Rf Type: General Purpose
• Secondary Attributes: I²C Interface
• Processor Series: XR18W750
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 400 KHz
• Number Of Timers: 1
• Operating Supply Voltage: 2.25 V to 3.63 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: XR18W750/753-0A-EB, XR18W750/753-0B-EB
• Minimum Operating Temperature: - 40 C
• Program Memory Type: EEPROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

XR18W750
WIRELESS UART CONTROLLER
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See
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LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR bit-4 selects the even or odd parity format.
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•
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
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•
•
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space", LOW state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
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•
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL and DLM) enable.
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The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
5.7
Logic 0 = No parity.
Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
LCR BIT-5 = logic 0, parity is not forced (default).
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
Logic 0 = No TX break condition (default).
Logic 1 = Forces the transmitter output (TX) to a “space”, LOW, for alerting the remote receiver of a line
break condition.
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers are selected.
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
Table 11
LCR B
X
0
0
1
1
IT
-5 LCR B
for parity selection summary below.
X
0
1
0
1
IT
-4 LCR B
T
ABLE
0
1
1
1
1
11: P
IT
-3
ARITY SELECTION
26
Forced parity to space, “0”
Force parity to mark, “1”
P
ARITY SELECTION
Even parity
Odd parity
No parity
REV. 1.0.0