XR18W750IL48-F Exar Corporation, XR18W750IL48-F Datasheet - Page 24

• Manufacturer Part Number: XR18W750IL48-F
• Description: IC WIRELESS UART CTRLR 48QFN
• Manufacturer: Exar Corporation

Specifications of XR18W750IL48-F

• Package / Case: 48-VFQFN Exposed Pad
• Function: Controller
• Rf Type: General Purpose
• Secondary Attributes: I²C Interface
• Processor Series: XR18W750
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 400 KHz
• Number Of Timers: 1
• Operating Supply Voltage: 2.25 V to 3.63 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: XR18W750/753-0A-EB, XR18W750/753-0B-EB
• Minimum Operating Temperature: - 40 C
• Program Memory Type: EEPROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

XR18W750
WIRELESS UART CONTROLLER
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•
•
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
•
•
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load.
must be set to ‘1’ before these bits can be accessed. Note that the receiver and the transmitter cannot use
different trigger tables. Whichever selection is made last applies to both the RX and TX side.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
The FCTR Bits 5-4 are associated with these 2 bits. These 2 bits are used to set the trigger level for the receive
FIFO. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the
trigger level.
different trigger tables. Whichever selection is made last applies to both the RX and TX side.
T
Table-A
Table-B
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
T
RIGGER
ABLE
FCTR
B
Table 10
IT
0
0
-5
T
ABLE
FCTR
B
IT
0
1
10: T
shows the complete selections. Note that the receiver and the transmitter cannot use
-4
RANSMIT AND
B
FCR
IT
0
0
1
1
0
0
1
1
-7
B
FCR
IT
0
1
0
1
0
1
0
1
-6
R
ECEIVE
B
FCR
IT
0
0
0
1
1
-5
FIFO T
BIT
FCR
24
0
0
1
0
1
-4
RIGGER
T
Table 10
RIGGER
1 (default)
R
ECEIVE
T
14
16
24
28
ABLE AND
4
8
8
L
EVEL
below shows the selections. EFR bit-4
L
1 (default)
T
EVEL
T
RANSMIT
RIGGER
L
EVEL
16
24
30
8
S
ELECTION
16C550, 16C2550,
16C2552, 16C554,
16C580
16C650A
C
OMPATIBILITY
REV. 1.0.0