PIC16F1828-I/SS Microchip Technology, PIC16F1828-I/SS Datasheet - Page 344
PIC16F1828-I/SS
Manufacturer Part Number
PIC16F1828-I/SS
Description
IC PIC MCU 8BIT 14KB FLSH 20SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16F1826-IP.pdf
(40 pages)
3.PIC16F1824-ISL.pdf
(2 pages)
4.PIC16F1824-ISL.pdf
(419 pages)
5.PIC16F1824-ISL.pdf
(10 pages)
Specifications of PIC16F1828-I/SS
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP (0.200", 5.30mm Width)
Controller Family/series
PIC16F
No. Of I/o's
18
Eeprom Memory Size
256Byte
Ram Memory Size
256Byte
Cpu Speed
32MHz
No. Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F1828-I/SS
Manufacturer:
MIC
Quantity:
20 000
- PIC16F722-ISS PDF datasheet
- PIC16F1826-IP PDF datasheet #2
- PIC16F1824-ISL PDF datasheet #3
- PIC16F1824-ISL PDF datasheet #4
- PIC16F1824-ISL PDF datasheet #5
- Current page: 344 of 419
- Download datasheet (4Mb)
CALL
Syntax:
Operands:
Operation:
Status Affected:
Description:
CALLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
CLRF
Syntax:
Operands:
Operation:
Status Affected:
Description:
CLRW
Syntax:
Operands:
Operation:
Status Affected:
Description:
2010 Microchip Technology Inc.
Call Subroutine
[ label ] CALL k
0 k 2047
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
None
Call Subroutine. First, return address
(PC + 1) is pushed onto the stack.
The eleven-bit immediate address is
loaded into PC bits <10:0>. The upper
bits of the PC are loaded from
PCLATH. CALL is a two-cycle instruc-
tion.
Clear W
[ label ] CLRW
None
00h (W)
1 Z
Z
W register is cleared. Zero bit (Z) is
set.
[ label ] CALLW
(PC) +1 TOS,
(W) PC<7:0>,
(PCLATH<6:0>) PC<14:8>
Subroutine call with W. First, the
return address (PC + 1) is pushed
onto the return stack. Then, the con-
tents of W is loaded into PC<7:0>,
and the contents of PCLATH into
PC<14:8>. CALLW is a two-cycle
instruction.
Subroutine Call With W
None
None
Clear f
[ label ] CLRF
0 f 127
00h (f)
1 Z
Z
The contents of register ‘f’ are cleared
and the Z bit is set.
f
Preliminary
CLRWDT
Syntax:
Operands:
Operation:
Status Affected:
Description:
COMF
Syntax:
Operands:
Operation:
Status Affected:
Description:
DECF
Syntax:
Operands:
Operation:
Status Affected:
Description:
PIC16(L)F1824/1828
Complement f
[ label ] COMF
0 f 127
d [0,1]
(f) (destination)
Z
The contents of register ‘f’ are com-
plemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Decrement f
[ label ] DECF f,d
0 f 127
d [0,1]
(f) - 1 (destination)
Z
result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
Clear Watchdog Timer
[ label ] CLRWDT
None
00h WDT
0 WDT prescaler,
1 TO
1 PD
TO, PD
CLRWDT instruction resets the Watch-
dog Timer. It also resets the prescaler
of the WDT.
Status bits TO and PD are set.
Decrement register ‘f’. If ‘d’ is ‘0’, the
f,d
DS41419B-page 343
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