TDA5101 Infineon Technologies, TDA5101 Datasheet - Page 17

• Manufacturer Part Number: TDA5101
• Description: TRANSMITTER ASK/FSK P-TSSOP-16
• Manufacturer: Infineon Technologies

Specifications of TDA5101

• Frequency: 315MHz
• Applications: Alarm Systems, Communication Systems
• Modulation Or Protocol: ASK, FSK
• Data Rate - Maximum: 20 kbps
• Power - Output: 5dBm
• Current - Transmitting: 7mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.1 V ~ 4 V
• Operating Temperature: -25°C ~ 85°C
• Package / Case: 16-TSSOP
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Product Depth (mm): 4.4mm
• Operating Supply Voltage (min): 2.1V
• Operating Supply Voltage (typ): 2.5/3.3V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: TDA5101INTR

TDA 5101
Functional Description
3.4.5 Power Modes
The IC provides three power modes, the POWER DOWN MODE, the PLL
ENABLE MODE and the TRANSMIT MODE.
3.4.5.1 Power Down Mode
In the POWER DOWN MODE the complete chip is switched off.
The current consumption is typically 0.3 nA at 3 V 25°C.
3.4.5.2 PLL Enable Mode
In the PLL ENABLE MODE the PLL is switched on but the power amplifier is
turned off to avoid undesired power radiation during the time the PLL needs to
settle. The turn on time of the PLL is determined mainly by the turn on time of
the crystal oscillator and is less than 1 msec when the specified crystal is used.
The current consumption is typically 3.5 mA.
3.4.5.3 Transmit Mode
In the TRANSMIT MODE the PLL is switched on and the power amplifier is
turned on too.
The current consumption of the IC is typically 7 mA when using a proper trans-
forming network at PAOUT, see Figure 4-1.
3.4.5.4 Power mode control
The bias circuitry is powered up via a voltage V > 1.5 V at the pin PDWN (pin 1).
When the bias circuitry is powered up, the pins ASKDTA and FSKDTA are
pulled up internally.
Forcing the voltage at the pins low overrides the internally set state.
Alternatively, if the voltage at ASKDTA or FSKDTA is forced high externally, the
PDWN pin is pulled up internally via a current source. In this case, it is not nec-
essary to connect the PDWN pin, it is recommended to leave it open.
The principle schematic of the power mode control circuitry is shown in
Figure 3-5.
Wireless Components
3 - 10
Specification, October 2001