MC13211 Freescale Semiconductor, MC13211 Datasheet
MC13211
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... Freescale Semiconductor, Inc., 2005, 2006, 2007, 2008, 2009. All rights reserved. Document Number: MC1321x Rev. 1.8 08/2009 MC1321x Package Information Case 1664-01 71-pin LGA [9x9 mm] Ordering Information Device Device Marking 1 MC13211 13211 1 MC13212 13212 1 MC13213 13213 1 See Table 1 for more details. ...
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... The MC1321x family is organized as follows: • The MC13211 has 16KB of flash and 1KB of RAM and is an ideal solution for low cost, proprietary applications that require wireless point-to-point or star network connectivity. The MC13211 combined with the Freescale Simple MAC (SMAC) provides the foundation for proprietary applications by supplying the necessary source code and application examples to get users started on implementing wireless connectivity ...
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... Considerations Reference Manual (ZHDCRM). Operating Device Temp Range Package (TA.) MC13211 -40° to 85° C LGA MC13211R2 -40° to 85° C LGA Tape and Reel MC13212 -40° to 85° C LGA MC13212R2 -40° to 85° C LGA Tape and Reel MC13213 -40° to 85° C LGA MC13213R2 -40° to 85° C LGA ...
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... Low voltage MCU with 40 MHz low power HCS08 CPU core • 60K flash memory with block protection and security and 4K RAM — MC13211: 16KB Flash, 1KB RAM — MC13212: 32KB Flash, 2KB RAM — MC13213: 60KB Flash, 4KB RAM • ...
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... Software Features Freescale provides a wide range of software functionality to complement the MC1321x hardware. There are three levels of application solutions: • SMAC • IEEE 802.15.4 Standard-Compliant MAC • SynkroRF • BeeStack • BeeStack Consumer (ZigBee RF4CE) Freescale Semiconductor MC13211/212/213 Technical Data, Rev. 1.8 5 ...
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... Based on the IEEE 802.15.4 Standard • Supports application profiles that define standardized command sets for multi-vendor interoperability • Supports vendor specific extensions to standard application profiles for vendor specific customizing • Supports AES-128 bit encryption 6 MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor ...
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... MCU for low power operation. This internal reference is approximately 243 kHz Freescale Semiconductor Analog Receiv er RFIC Timers Frequency Generator Digital Control Logic Analog Transmitter Buffer RAM RAM Arbiter Voltage Regulators 802.15.4 Modem MC13211/212/213 Technical Data, Rev. 1.8 Background HCS08 CPU Debug Module 16- Channel Flash Memory 10 Bit ADC 1-4 KB RAM 2x SCI Dedicated I C ...
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... XTAL1 XTAL2 CLKO EXTAL 16MHz MC1321x 71 TES T Flag opening Flag opening TES Figure 3. MC1321x Pinout (Top View) MC13211/212/213 Technical Data, Rev. 1.8 XTAL PTD4/TPM2CH1 48 47 PTD2/TPM1CH2 70 ATTN 46 VDD 45 GPIO1 44 43 GPIO2 GPIO3 42 GPIO4 PAO_M PAO_P RFIN_P 36 RFIN_M 35 34 CT_Bias VDDA 33 29 ...
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... MCU reset. Active low MCU Port C Bit 0 / SCI2 TX data out MCU Port C Bit 1/ SCI2 RX data in MCU Port C Bit 1/ IIC bus data MCU Port C Bit 1/ IIC bus clock MCU Port C Bit 4 MCU Port C Bit 5 MCU Port C Bit 6 MC13211/212/213 Technical Data, Rev. 1.8 Functionality 9 ...
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... When used with internal T/R switch, this is a negative bi-directional RF port for the internal LNA and PA Modem RF input/output When used with internal T/R switch, this is a positive bi-directional RF port for the internal LNA and PA Not used May be grounded or left open MC13211/212/213 Technical Data, Rev. 1.8 Functionality Freescale Semiconductor ...
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... Channel 3 MCU Port D Bit 7 / TPM2 Channel 4 MCU Port B Bit 0 / ATD analogChannel 0 MCU Port B Bit 1 / ATD analog Channel 1 MCU Port B Bit 2 / ATD analog Channel 2 MCU Port B Bit 3 / ATD analog Channel 3 MCU Port B Bit 4 / ATD analog Channel 4 MC13211/212/213 Technical Data, Rev. 1.8 Functionality 11 ...
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... Normally factory test. Do not connect the RXTXEN input to the modem to enable CCA operations. MCU Port D Bit 3 drives Normally factory test. Do not connect the reset M_RST input to the modem. External package flag. Connect to ground. Common VSS MC13211/212/213 Technical Data, Rev. 1.8 Functionality Freescale Semiconductor ...
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... Modem interrupt request M_IRQ output drives MCU IRQ input 1 MCU Port D Bit 1 drives the RXTXEN input to the modem to enable CCA operations. MCU Port D Bit 3 drives the reset M_RST input to the modem. NOTE MC13211/212/213 Technical Data, Rev. 1.8 Description Table 3, the MCU needs 13 ...
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... MCU SPI master SPI clock output drives modem SPICLK slave clock input. MCU SPI master MOSI output drives modem slave MOSI input Modem SPI slave MISO output drives MCU master MISO input MCU SPI master SS output drives modem slave CE input MC13211/212/213 Technical Data, Rev. 1.8 Figure 4 shows the SiP interconnections 11 ...
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... The SPSCK signal is a clock output from the master and an input to the slave. The slave device must be selected by a low level on the slave select input (SS1 pin). Freescale Semiconductor MOS1 MOSI 0 MISO1 MISO SPSCK1 SPICLK PTE2/SS1 CE Figure 5. SPI System Block Diagram MC13211/212/213 Technical Data, Rev. 1.8 MODEM (SLAVE) SPI SHIFTER ...
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... Prescaler 4 Programmable Timer Comparators Transmit Synthesizer Packet RAM 2 Transmit Packet RAM 1 2.45 GHz VCO Transmit RAM FCS Header Generation Generation MC13211/212/213 Technical Data, Rev. 1.8 Analog Regulator Pow er-Up Digital Control Regulator L Logic Packet Digital Processor Regulator H Cry stal Regulator VCO ...
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... CCA reported power level versus input power. Note that CCA reported power saturates at about -57 dBm input power which is well above 802.15.4 Standard requirements. Freescale Semiconductor 1 byte 125 bytes maximum FLI Payload Data Figure 7. 802.15.4 modem Packet Structure MC13211/212/213 Technical Data, Rev. 1.8 2 bytes FCS 17 ...
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... Figure 9. Reported Power Level Versus Input Power for Energy Detect or Link Quality Indicator 18 NOTE 802.15.4 Ac curac y and range Requirements -80 -70 -60 Input Pow er (dBm) 802.15.4 Accuracy and Range Requirements -75 -65 -55 -45 -35 MC13211/212/213 Technical Data, Rev. 1.8 -50 -25 -15 Freescale Semiconductor ...
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... Crystal Reference Oscillator On. Receiver On. Transmit Crystal Reference Oscillator On. Transmitter On. Freescale Semiconductor Table 5. Current drain in the various modes is listed in Definition MC13211/212/213 Technical Data, Rev. 1.8 Transition Time To or From Idle Idle Idle (300 + 1/CLKO) µs to Idle 144 µs from Idle 144 µs from Idle ...
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... SPI burst is shown in because the modem is limited by this number SPICLK Valid MISO MOSI Valid 20 NOTE Figure 10. The maximum SPI clock rate is 8 Mhz from the MCU SPI Burst Figure 10. SPI Single Burst Timing Diagram MC13211/212/213 Technical Data, Rev. 1 Freescale Semiconductor ...
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... After the final SPI burst negated to high to signal the end of the transaction. An example SPI read transaction with a 2-byte payload is shown in CE Clock Burst SPICLK MISO MOSI Freescale Semiconductor Valid Valid Header Read data Figure 11. SPI Read Transaction Diagram MC13211/212/213 Technical Data, Rev. 1.8 Figure 11. Valid 21 ...
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... The modem uses the 16 MHz crystal oscillator as the reference oscillator for the system and a programmable warp capability is provided controlled by programming CLKO_Ctl Register 0A, Bits 22 MC1321X 802.15.4 MODEM XTAL1 XTAL2 CLKO 16MHz Figure 12. Modem Crystal Oscillator MC13211/212/213 Technical Data, Rev. 1.8 Figure 12. Freescale Semiconductor ...
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... An external antenna switch is used to multiplex the antenna between receive and transmit. An LNA is in the receive path to add gain for greater receive sensitivity. Two external baluns are required to convert the single-ended antenna switch signals to the differential signals Freescale Semiconductor 50 100 150 200 xtal_trim[7:0] (decimal) MC13211/212/213 Technical Data, Rev. 1.8 250 300 23 ...
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... Figure 14. Using the MC1321x with External RF Components MC1321x 14B) Using External Antenna Switch With LNA L2 L3 RFIN_P (PAO_P) RFIN_M (PAO_M) VDDA Bypass Bypass L4 L5 CT_Bias PAO_P PAO_M 14C) Using Dual Antennae MC13211/212/213 Technical Data, Rev. 1 IN_ lun 1321x tl lun MC1321x Freescale Semiconductor ...
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... IIC MODULE (IIC) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI1) SERIAL COMMUNICATIONS INTERFACE MODULE (SCI2) 1-CHANNEL TIMER/PWM MODULE (TPM1) 4-CHANNEL TIMER/PWM MODULE (TPM2) DEDICATED SERIAL PERIPHERAL INTERFACE MODULE (SPI) MC13211/212/213 Technical Data, Rev. 1.8 8 PTA7/KBI1P7– PTA0/KBI1P0 8 PTB7/AD1P7– PTB0/AD1P0 PTC7 PTC6 PTC5 PTC4 PTC3/SCL1 ...
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... The Stop2 Mode provides very low standby power consumption and maintains the contents of RAM and the current state of all of the I/O pins. Stop2 can be entered only if the LVD circuit is not enabled in Stop Modes (either LVDE or LVDSE not set). 26 NOTE MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor ...
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... Stop2. Instead they are maintained by virtue of the states of the internal logic driving the pins being maintained. Exit from Stop3 is performed by asserting RESET, an asynchronous interrupt pin, or through the real-time interrupt. The asynchronous interrupt pins are the IRQ or KBI pins. Freescale Semiconductor MC13211/212/213 Technical Data, Rev. 1.8 27 ...
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... HIGH PAGE REGISTERS $182B $182C UNIMPLEMENTED 26580 BYTES $7FFF $8000 FLASH 32768 BYTES $FFFF MC13212 Figure 16. MC1321X Memory Maps MC13211/212/213 Technical Data, Rev. 1.8 $0000 DIRECT PAGE REGISTERS $007F $0080 RAM 1024 BYTES $047F $0480 UNIMPLEMENTED 4992 BYTES $17FF $1800 HIGH PAGE REGISTERS ...
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... CLKO as external source, maximum FLL frequency is 32 MHz (16 MHz bus rate) with CLKO = 16 MHz or maximum FLL frequency is 40 MHz (20 MHz bus rate) with CLKO = 4 MHz. Freescale Semiconductor Figure 17, the ICG consists of four functional blocks. MC13211/212/213 Technical Data, Rev. 1.8 29 ...
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... The ICG’s FLL is used to generate frequencies that are programmable multiples of the external clock reference. — FLL engaged external unlocked is a transition state which occurs while the FLL is attempting to lock. The FLL DCO frequency is off target and the FLL is adjusting the DCO to match the target frequency. 30 MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor ...
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... REF LOOP (FLL) SELECT LOSS OF LOCK AND CLOCK DETECTOR IRG ICGIRCLK TYP 243 kHz 8 MHz LOCAL CLOCK FOR OPTIONAL USE WITH BDC RG Figure 17. ICG Block Diagram MC13211/212/213 Technical Data, Rev. 1.8 CLOCK SELECT OUTPUT CLOCK ICGDCLK /R SELECT ICGOUT FIXED CLOCK SELECT ...
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... INDEX REGISTER H:X H INDEX REGISTER (HIGH CONDITION CODE REGISTER ACCUMULATOR A INDEX REGISTER (LOW STACK POINTER PROGRAM COUNTER CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 18. CPU Registers MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor ...
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... SS signal to have the proper use to support the modem transaction protocol for the modem CE signal. Freescale Semiconductor NOTE Figure 15). These port I/O signals should be MC13211/212/213 Technical Data, Rev. 1.8 33 ...
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... Figure 19. Modem Dedicated SPI Block Diagram 34 SHIFT IN SPC0 BIDIROE Rx BUFFER Tx BUFFER FULL CLOCK EMPTY MASTER CLOCK SLAVE CLOCK LOGIC MOD- SSOE SPTEF SPRF SPTIE MODF SPIE MC13211/212/213 Technical Data, Rev. 1.8 PIN CONTROL M MOSI MOSI S M MISO MISO S MODEM SPI PORT M SPSCK SPICLK S MASTER/ SLAVE SS CE ...
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... KBI module. KBIP0 KBIPE0 KBIP3 KBIPE3 1 KBIP4 0 S KBIPE4 KBEDG4 1 KBIPn 0 S KBIPEn KBEDGn Freescale Semiconductor VDD CLR KEYBOARD INTERRUPT FF KBIMOD Figure 20. KBI Block Diagram MC13211/212/213 Technical Data, Rev. 1.8 BUSCLK KBACK RESET KBF SYNCHRONIZER STOP BYPASS STOP KEYBOARD INTERRUPT REQUEST KBIE 35 ...
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... The TPM shares its I/O pins with general-purpose I/O port pins. Figure 21 one TPM, with various numbers of channels. 36 shows the structure of a TPM. Some MCUs include more than MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor ...
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... CLOCK SOURCE SELECT OFF, BUS, XCLK, EXT CLKSB CLKSA COUNTER RESET ELS1B ELS1A CH1F CH1IE MS1B MS1A Figure 21. TPM Block Diagram MC13211/212/213 Technical Data, Rev. 1.8 PRESCALE AND SELECT DIVIDE 16, 32, 64, or 128 PS2 PS1 PS0 TOF INTERRUPT LOGIC TFIE TPM1CH1 PORT ...
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... The transmitter and receiver operate independently, although they use the same baud rate generator. During normal operation, the MCU monitors the status of the SCI, writes the data to be transmitted, and processes received data. Figure 22 38 and Figure 23 show the SCI transmitter and receiver block diagrams. MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor ...
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... TRANSMIT SHIFT REGISTER SHIFT DIRECTION T8 PARITY GENERATION TRANSMIT CONTROL SBK TDRE TIE TC TCIE Figure 22. SCI Transmitter MC13211/212/213 Technical Data, Rev. 1.8 LOOPS RSRC LOOP TO RECEIVE CONTROL DATA IN TO TxD1 PIN SCI CONTROLS TxD1 TxD1 DIRECTION Tx INTERRUPT REQUEST TO TxD1 PIN LOGIC 39 ...
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... PT 40 (READ-ONLY) SCID – Rx BUFFER DIVIDE 11-BIT RECEIVE SHIFT REGISTER WAKE WAKEUP LOGIC ILT RDRF RIE IDLE ILIE OR ORIE FE FEIE NF NEIE PARITY PF CHECKING PEIE Figure 23. SCI Receiver MC13211/212/213 Technical Data, Rev. 1 SHIFT DIRECTION RWU Rx INTERRUPT REQUEST ERROR INTERRUPT REQUEST Freescale Semiconductor ...
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... The module will continue to operate while the MCU is in wait mode and can provide a wake-up interrupt. Stop mode The IIC is inactive in Stop3 Mode for reduced power consumption. The STOP instruction does not affect IIC register states. Stop1 and Stop2 will reset the register contents. Freescale Semiconductor MC13211/212/213 Technical Data, Rev. 1.8 41 ...
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... IIC module. ADDRESS ADDR_DECODE CTRL_REG INPUT SYNC CLOCK CONTROL 42 FREQ_REG ADDR_REG STATUS_REG START STOP ARBITRATION CONTROL SDA SCL Figure 24. IIC Functional Block Diagram MC13211/212/213 Technical Data, Rev. 1.8 DATA BUS INTERRUPT DATA_MUX DATA_REG IN/OUT DATA SHIFT REGISTER ADDRESS COMPARE Freescale Semiconductor ...
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... Upon setting the ATDPU bit, the module is reactivated. During power-down mode, the ATD registers are still accessible. The reset state of the ATDPU bit is zero. Therefore, the module is reset into the power-down state. Freescale Semiconductor NOTE MC13211/212/213 Technical Data, Rev. 1.8 43 ...
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... DATA JUSTIFICATION CTL STATUS CONVERSION MODE CONTROL BLOCK POWERDOWN SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER (ATD) BLOCK = INTERNAL PINS = CHIP PADS Figure 25. ATD Block Diagram MC13211/212/213 Technical Data, Rev. 1.8 SAR_REG <9:0> RESULT REGISTERS CTL STATE MACHINE DIGITAL ANALOG CTL Freescale Semiconductor ...
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... Flexible 8-word by 16-bit FIFO (first-in, first-out) buffer for capture information: — Change-of-flow addresses or — Event-only data • Two types of breakpoints: — Tag breakpoints for instruction opcodes — Force breakpoints for any address access • Nine trigger modes: Freescale Semiconductor MC13211/212/213 Technical Data, Rev. 1.8 45 ...
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... Note: Meets Human Body Model (HBM kV. RF input/output pins have no ESD protection. 46 Table 6 may affect device reliability or cause permanent Table 6. LGA Package Maximum Ratings Symbol V BATT MC13211/212/213 Technical Data, Rev. 1 the programmable SS DD Value T 125 J T -55 to 125 stg , V -0.3 to 3.6 ...
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... DD > greater than I , the injection current may flow out Symbol BATT, V DDINT SPI P max f ref MC13211/212/213 Technical Data, Rev. 1.8 DD load will shunt current greater than maximum DD Min Typ Max 2.0 2.7 3.4 2.405 - 2.480 - 30% V DDINT 70 DDINT V DDINT - - 8 ...
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... Table 8. DC Electrical Characteristics , °C, unless otherwise noted) DDINT A Symbol ) I leakage I CCH I CCD I CCI I CCT I CCR NOTE = 2 ° MHz, unless otherwise noted.) A ref MC13211/212/213 Technical Data, Rev. 1.8 Min Typ Max - 0.2 1.0 - 1.0 6 102 - 500 800 - ± 30% V DDINT 70 DDINT V DDINT ...
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... Symbol P out EVM VDDA Z4 C13 3 1 C17 2 5 10pF 1.0pF 4 6 LDB212G4005C-001 C12 10pF Z5 C14 3 1 C18 2 5 10pF 1.8pF 4 6 LDB212G4005C-001 Figure 26. RF Parametric Evaluation Circuit MC13211/212/213 Technical Data, Rev. 1.8 Symbol Min Typ Max - - 200 - - Min Typ Max - - 250 - ...
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... DD V LVWL (V falling rising) DD (2) V Rearm MC13211/212/213 Technical Data, Rev. 1.8 Symbol Typ Unit Ω Zin 16.2 - j139 16.0 – j136 15.7 – j133 Ω Zin 12.6 – j93.7 12.5 – j91.4 12.4 – j89.3 Ω Zin 18.5 – j148 18.3 – j146 18.2 – ...
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... DD > greater than I , the injection current may flow out load will shunt current greater than maximum injection DD and MC13211/212/213 Technical Data, Rev. 1.8 1 Min Typical Max 0.35 × V — 0.30 × V — 0.06 × V — — ...
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... MHz) Bus Stop1 mode supply current Stop2 mode supply current not drive IRQ above NOTE (Temperature Range = –40 to 85°C Ambient) Symbol S1I DD S2I DD MC13211/212/213 Technical Data, Rev. 1 (V) Typical Max DD (4) 2.1 mA (4) 3 1.1 mA 2.1 mA (4) 2.1 mA (4) 1.8 mA (4) 2 ...
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... Values given under the following conditions: low range operation (RANGE = 0), low power mode (HGO = 0), clock monitor disabled (LOCD = 1) Freescale Semiconductor (Temperature Range = –40 to 85°C Ambient) Symbol S3I MHz. Bus MC13211/212/213 Technical Data, Rev. 1 (V) Typical Max DD 4.3 μA (4) 7.2 μA ...
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... V < V DDAD DDAD 2.08V Enabled I REF Disabled I REF (ATDPU = 0 or STOP INDC SSAD . DD MC13211/212/213 Technical Data, Rev. 1.8 Typical Max — 3.6 — 0.7 1.2 — 0.02 0.6 — — 100 — — 100 — — V SSAD — ...
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... DDAD CC Bus Cycles = ((PRS+1)*2) * (28) and V for valid conversion. Values greater than V REFH –V )/1024 REFH REFL –V )). REFH REFL –V )). REFH REFL MC13211/212/213 Technical Data, Rev. 1.8 1 Min Typ Max 0.5 — 2.0 0.5 — 1 <30 14.0 — 60.0 28.0 — ...
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... T IL ICG EXTAL R F Crystal or Resonator (See Note NOTE: Use fundamental mode crystal or ceramic resonator only. Figure 27. ICG Clock Basic Schematic Symbol Min MC13211/212/213 Technical Data, Rev. 1.8 XTAL Typ Max Unit 2 10 MΩ Ω 0 Freescale Semiconductor ...
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... ICGOUT f Extal ICGDCLKmin f ICGDCLKma Self ICGDCLKmin f Self_reset f LOR f LOD t CSTL t CSTH t Lockl t Lockh n Unlock n Lock MC13211/212/213 Technical Data, Rev. 1.8 Min Typical Max 32 — 100 2 — — — 100 2 — — 40 243 303.75 40 — 60 (min) f (max) Extal (min) f ICGDCLKma (max) ...
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... SSA Table 18. MCU Control Timing Symbol f Bus t RTI t extrst t rstdrv t MSSU t MSH t ILIH Rise Fall MC13211/212/213 Technical Data, Rev. 1.8 Min Typical Max — 0.2 ± 0.5 ±2 — ±0.5 ±2 — percentage Jitter Min Typical Max dc — 20 700 1300 1.5 x — ...
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... Figure 29. Control Active Background Debug Mode Latch Timing Freescale Semiconductor and 80% V levels. Temperature range –40°C to 85° extrst Figure 28. Control Reset Timing RESET t MSSU t ILIH IRQ Figure 30. Control IRQ Timing MC13211/212/213 Technical Data, Rev. 1.8 and then samples the Self_reset t MSH 59 ...
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... TPMext t 1.5 clkh t 1.5 clkl t 1.5 ICPW t Text t clkh t clkl Figure 31. Timer External Clock t ICPW t ICPW Figure 32. Timer Input Capture Pulse MC13211/212/213 Technical Data, Rev. 1.8 Max Unit f /4 MHz Bus — t cyc — t cyc — t cyc — t cyc Freescale Semiconductor ...
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... SCK t Lead t Lag t WSCK BIT BIT Figure 33. SPI Master Timing (CPHA = 0) MC13211/212/213 Technical Data, Rev. 1.8 Min Max /2048 MHz Bus Bus 2 2048 1/2 — 1/2 — 62.5 1024 t cyc 15 — 0 — — — — t – 25 cyc — 25 — t – 25 cyc — ...
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... Engineering Bulletin EB618/D, Typical Data Retention for Non-volatile Memory. 62 Table 21. FLASH Characteristics Symbol V prog/erase V Read f FCLK t Fcyc (2) t prog t Burst t Page t Mass 10,000 t D_ret MC13211/212/213 Technical Data, Rev. 1.8 Min Typical Max 2.1 3.6 1.8 3.6 2.08 3.6 150 200 5 6. 4000 20,000 — 100,000 — 15 100 — ...
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... The on-chip trim capability may be used to determine the closest standard value by adjusting the trim value via the SPI and observing the frequency at CLKO. Each internal trim load capacitor has a trim range of approximately steps. Initial tolerance for the internal trim capacitance is approximately ±15%. Freescale Semiconductor MC13211/212/213 Technical Data, Rev. 1.8 63 ...
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... Figure 34. MC1321x Modem Crystal Circuit Table 22. MC1321x Crystal Specifications Value Unit 16.000000 MHz 2 ± 10 ppm 3 ± 15 ppm ± 2 ppm Ω MC13211/212/213 Technical Data, Rev. 1.8 C10 6.8pF C11 6.8pF Table 22. A number of the stated 1 Condition at 25 °C Over desired temperature range max max Freescale Semiconductor ...
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... CLKO - is always an output. During Hibernate CLKO retains its output state, but does not toggle. During Doze, CLKO may toggle depending on whether it is being used. Freescale Semiconductor Value Unit <2 pF max fundamental NOTE MC13211/212/213 Technical Data, Rev. 1.8 1 (continued) Condition 65 ...
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... Passive component values can vary as a function of circuit board layout as required to obtain best matching and RF performance GPIO1 39 PAO_M 38 1.5nH PAO_P 36 RFIN_P 35 L2 RFIN_M 34 3.9nH CT_Bias L4 MC1321x 1.5nH Figure 35. RF Single Port Application with an F-Antenna 66 NOTE LDB212G4005C-001 3.9nH 1.0pF C2 10pF MC13211/212/213 Technical Data, Rev. 1 Not Mounted ANT1 F_Antenna SMA_edge_Receptacle_Female 5 Freescale Semiconductor ...
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... Figure 36. RF Dual Port Application with an F-Antenna Freescale Semiconductor NOTE VDDA 10pF 1.0pF 4 6 IC1 LDB212G4005C-001 3 OUT2 1 OUT1 C6 2 GND 10pF VCONT µPG2012TK- 10pF 1.8pF 4 6 LDB212G4005C-001 MC13211/212/213 Technical Data, Rev. 1 VDD 10pF 2.2nH 1.8pF 0R Not Mounted SMA_edge_Receptacle_Female 5 ANT2 F_Antenna 67 ...
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... Mechanical Diagrams Figure 37 and Figure 38 show the MC1321x mechanical information. 68 Figure 37. MC1321x Mechanical ( MC13211/212/213 Technical Data, Rev. 1.8 Freescale Semiconductor ...
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... Freescale Semiconductor Figure 38. MC1321x Mechanical ( MC13211/212/213 Technical Data, Rev. 1.8 69 ...
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... Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase ...