SI4421-A0-FT Silicon Laboratories Inc, SI4421-A0-FT Datasheet - Page 31

• Manufacturer Part Number: SI4421-A0-FT
• Description: IC TXRX FSK 915MHZ 3.8V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4421-A0-FT

• Frequency: 433MHz, 868MHz, 915MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK
• Applications: ISM
• Power - Output: 7dbm
• Sensitivity: -110dBm
• Voltage - Supply: 2.2 V ~ 3.8 V
• Current - Receiving: 15mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1737-5

RX FIFO BUFFERED DATA READ
In this operating mode, incoming data are clocked into a 16-bit FIFO buffer. The receiver starts to fill up the FIFO when the Valid Data
Indicator (VDI) bit and the synchron pattern recognition circuit indicates potentially real incoming data. This prevents the FIFO from
being filled with noise and overloading the external microcontroller.
Interrupt Controlled Mode:
The user can define the FIFO IT level (the number of received bits) which will generate the nFFIT when exceeded. The status bits
report the changed FIFO status in this case.
Polling Mode:
When nFFS signal is low the FIFO output is connected directly to the SDO pin and its content can be clocked out by the SCK. Set the
FIFO IT level to 1. In this case, as long as FFIT indicates received bits in the FIFO, the controller may continue to take the bits away.
When FFIT goes low, no more bits need to be taken.
An SPI read command is also available to read out the content of the FIFO (Receiver FIFO Read Command, page 21).
FIFO Read Example with FFIT Polling
Note: During FIFO access f
RECOMMENDED PACKET STRUCTURES
Recommended length
Minimum length
clock signal is not 50% the shorter period of the clock pulse should be at least 2/f
8 -12 bits (e.g. AAh or 55h)
SCK
4 - 8 bits (1010b or 0101b)
cannot be higher than f
Preamble
nSEL
nFFS
SDO
SCK
FFIT
FIFO OUT
ref
0
/4, where f
2DD4h (D4 is programmable)
FO+1
(Can be network ID)
D4h (programmable)
1
Synchron word
FIFO read out
FO+2
ref
2
is the crystal oscillator frequency. When the duty-cycle of the
FO+3
3
FO+4
4
ref
.
Payload
?
?
4 bit - 1 byte
2 byte
CRC
Si4421
31