SI4421-A0-FT Silicon Laboratories Inc, SI4421-A0-FT Datasheet - Page 20

• Manufacturer Part Number: SI4421-A0-FT
• Description: IC TXRX FSK 915MHZ 3.8V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4421-A0-FT

• Frequency: 433MHz, 868MHz, 915MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK
• Applications: ISM
• Power - Output: 7dbm
• Sensitivity: -110dBm
• Voltage - Supply: 2.2 V ~ 3.8 V
• Current - Receiving: 15mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1737-5

Bits 2-0 (f2 to f0):
7. FIFO and Reset Mode Command
Bits 7-4 (f3 to f0):
Bit 3 (sp):
Note: The synchron pattern consists of one or two bytes depending on the sp bit. Byte1 is fixed 2Dh, Byte0 can be programmed by
Bit 2 (al):
Bit
the Synchron Pattern Command (page 21).
15
1
14
1
The Data Quality Detector is a digital processing part of the radio, connected to the demodulator - it is an indicator
reporting the reception of an FSK modulated RF signal. It will work every time the receiver is on. Setting this
parameter defines how clean incoming data stream would be stated as good data (valid FSK signal).
If the internally calculated data quality value exceeds the DQD threshold parameter for five consecutive data bits
for both the high and low periods, then the DQD signal goes high.
The DQD parameter in the Data Filter Command should be chosen according to the following rules:
13
0
Select the length of the synchron pattern:
DQD threshold parameter.
FIFO IT level. The FIFO generates IT when the number of received data bits reaches this level.
Set the input of the FIFO fill start condition:



sp
0
1
12
0
The DQD parameter can be calculated with the following formula:
DQD
It should be larger than 4 because otherwise noise might be treated as a valid FSK signal
The maximum value is 7.
par
11
1
= 4 x (deviation – TX-RX
10
Not used
0
Byte1
2Dh
9
1
al
0
1
8
0
FIFO fill start condition
Byte0 (POR)
f3
7
offset
Synchron pattern
D4h
D4h
) / bit rate
Always fill
f2
6
f1
5
Synchron Pattern (Byte1+Byte0)
f0
4
sp
3
2DD4h
al
2
D4h
1
ff
dr
0
CA80h
POR
Si4421
20