ATA5824-PLQW Atmel, ATA5824-PLQW Datasheet - Page 56

• Manufacturer Part Number: ATA5824-PLQW
• Description: IC TXRX UHF ASK/FSK 48QFN
• Manufacturer: Atmel

Specifications of ATA5824-PLQW

• Frequency: 433 ~ 435MHz; 866 ~ 870MHz
• Data Rate - Maximum: 20kbps
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, TPM, Security Systems
• Power - Output: 10dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.15 V ~ 3.6 V or 4.4 V ~ 5.25 V
• Current - Receiving: 10.5mA
• Current - Transmitting: 10.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

Figure 14-4. Timing Diagram During Bit-check
56
Bit-check counter
ATA5823/ATA5824
(Lim_min = 14, Lim_max = 24)
RX_ACTIVE
Demod_Out
Bit-check
T
Start-up mode
Startup_Sig_Proc
For the best noise immunity it is recommended to use a low span between T
This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A
“11111...” or a “10101...” sequence in Manchester or bi-phase is a good choice concerning that
advice. A good compromise between sensitivity and susceptibility to noise regarding the
expected edge to edge time t
time window should be ±50% and then N
edge to edge time periods, the Bit-check limits must be programmed according to the required
span.
The Bit-check limits are determined by means of the formula below:
Lim_min is defined by the bits Lim_min 0 to Lim_min 5 in control register 5.
Lim_max is defined by the bits Lim_max 0 to Lim_max 5 in control register 6.
Using the above formulas, Lim_min and Lim_max can be determined according to the required
T
minimum edge to edge time t
The lower limit should be set to Lim_min
Lim_max = 63.
Figure
limits Lim_min = 14 and Lim_max = 24. The signal processing circuits are enabled during
T
fined during that period. When the Bit-check becomes active, the Bit-check counter is clocked
with the cycle T
Figure 14-4
the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In
page 57
also fails if CV_Lim reaches Lim_max. This is illustrated in
Lim_min
Startup_PLL
0
14-4,
, T
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 101112131415161718 1 2 3 4 5 6 7 8 9 10 11
the Bit-check fails as the value CV_Lim is lower than the limit Lim_min. The Bit-check
Lim_max
and T
shows how the Bit-check proceeds if the Bit-check counter value CV_Lim is within
Figure 14-5
XDCLK
T
Startup_Sig_Proc
and T
XDCLK
.
XDCLK
and
. The time resolution defining T
ee
. The output of the ASK/FSK demodulator (Demod_Out) is unde-
ee
Figure 14-6 on page 57
is defined according to the section
1/2 Bit
is a time window of ±38%. To get the maximum sensitivity the
Bit-check
Bit-check mode
Bit check ok
T
Bit-check
10. The maximum value of the upper limit is
6. Using preburst patterns that contain various
T
T
illustrate the Bit-check for the Bit-check
Lim_min
Lim_max
1/2 Bit
Figure 14-6 on page
Lim_min
= Lim_min
= (Lim_max -1)
“Receiving Mode” on page
12131415 1 2 3 4 5 6 7
and T
Bit check ok
Lim_max
Lim_min
T
1/2 Bit
XDCLK
57.
is T
Figure 14-5 on
T
4829D–RKE–06/06
and T
XDCLK
XDCLK
Lim_max
. The
58.
.