ATA5824-PLQW Atmel, ATA5824-PLQW Datasheet - Page 53

• Manufacturer Part Number: ATA5824-PLQW
• Description: IC TXRX UHF ASK/FSK 48QFN
• Manufacturer: Atmel

Specifications of ATA5824-PLQW

• Frequency: 433 ~ 435MHz; 866 ~ 870MHz
• Data Rate - Maximum: 20kbps
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, TPM, Security Systems
• Power - Output: 10dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.15 V ~ 3.6 V or 4.4 V ~ 5.25 V
• Current - Receiving: 10.5mA
• Current - Transmitting: 10.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

14.1.2
14.1.3
4829D–RKE–06/06
Sleep Mode
Start-up Mode
To save current it is recommended CLK be disabled during RX polling mode. I
the current of the Microcontroller_Interface I
the current consumption is calculated as follows:
During T
nals. To guarantee the reception of a transmitted command the transmitter must start the
telegram with an adequate preburst. The required length of the preburst T
polling parameters T
actual bit rate and the number of bits (N
The length of period T
factor X
culated to be:
In US and European applications, the maximum value of T
(which is done by setting the bit X
1.2 ms in that case. The sleep time can be extended to about 300 ms by setting X
(which is done by setting X
9.6 ms.
During T
circuit starts up (T
ready to receive.
I
T
T
S_Poll
Preburst
Sleep
=
=
Sleep
I
Sleep
Sleep
Startup_PLL
Poll
T
Sleep
+
defined by the bit X
, T
I
VSINT
Startup_PLL
+
1024
T
Startup_PLL
the PLL is enabled and starts up. If the PLL is locked, the signal processing
Startup_Sig_Proc
Sleep
Sleep
T
, T
DCLK
and T
is defined by the 5-bit word sleep in control register 4, the extension
Startup_PLL
+
Sleep
T
Startup_Sig_Proc
Startup_Sig_Proc
Sleep
X
). After the start-up time all circuits are in stable condition and
Sleep
in control register 4 to 1), the time resolution is then about
Sleep
, T
in control register 4 and the basic clock cycle T
Startup_Sig_Proc
Bit-check
in control register 4 to 0). The time resolution is about
+
VSINT
the transceiver is not sensitive to a transmitter sig-
T
) to be tested.
Bitcheck
. If CLK is enabled during the RX polling mode
and T
Bit-check
Sleep
ATA5823/ATA5824
is about 38 ms if X
. Thus, T
Bit-check
Preburst
P
does not include
depends on the
depends on the
Sleep
DCLK
is set to 1
Sleep
. It is cal-
to 8
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