ATMEGA256RZAV-8MU Atmel, ATMEGA256RZAV-8MU Datasheet - Page 30
ATMEGA256RZAV-8MU
Manufacturer Part Number
ATMEGA256RZAV-8MU
Description
MCU ATMEGA2561/AT86RF230 64-QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA640V-8CU.pdf
(38 pages)
2.ATMEGA640V-8CU.pdf
(444 pages)
3.AT86RF230-ZU.pdf
(98 pages)
Specifications of ATMEGA256RZAV-8MU
Frequency
2.4GHz
Modulation Or Protocol
802.15.4 Zigbee
Applications
ISM, ZigBee™
Power - Output
3dBm
Sensitivity
-101dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
15.5mA
Current - Transmitting
16.5mA
Data Interface
PCB, Surface Mount
Memory Size
256kB Flash, 4kB EEPROM, 8kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
64-QFN
Wireless Frequency
2.4 GHz
Interface Type
JTAG, SPI
Output Power
3 dBm
For Use With
ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Data Rate - Maximum
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
ATmega256
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
ATMEGA256RZAV-8MU
Manufacturer:
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Quantity:
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8.1.3
8.1.4
2549M–AVR–09/10
Pull-up and Bus-keeper
Timing
Figure 8-2.
The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to
one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by
writing the Port register to zero before entering sleep.
The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be dis-
abled and enabled in software as described in
on page
these lines are tri-stated by the XMEM interface.
External Memory devices have different timing requirements. To meet these requirements, the
XMEM interface provides four different wait-states as shown in
tant to consider the timing specification of the External Memory device before selecting the wait-
state. The most important parameters are the access time for the external memory compared to
the set-up requirement. The access time for the External Memory is defined to be the time from
receiving the chip select/address until the data of this address actually is driven on the bus. The
access time cannot exceed the time from the ALE pulse must be asserted low until data is stable
during a read sequence (See t
378 - 381). The different wait-states are set up in software. As an additional feature, it is possible
to divide the external memory space in two sectors with individual wait-state settings. This
makes it possible to connect two different memory devices with different timing requirements to
the same XMEM interface. For XMEM interface timing details, please refer to
page 378
in the
Note that the XMEM interface is asynchronous and that the waveforms in the following figures
are related to the internal system clock. The skew between the internal and external clock
(XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Conse-
quently, the XMEM interface is not suited for synchronous operation.
“External Data Memory Timing” on page
38. When enabled, the bus-keeper will keep the previous value on the AD7:0 bus while
to
Table 30-16 on page 381
External SRAM Connected to the AVR
AVR
AD7:0
A15:8
ALE
WR
RD
LLRL
ATmega640/1280/1281/2560/2561
+ t
RLRH
and
- t
Figure 30-9 on page 381
DVRH
D
G
“XMCRB – External Memory Control Register B”
378.
in Tables 30-9 through Tables 30-16 on pages
Q
Table 8-3 on page
D[7:0]
A[15:8]
A[7:0]
RD
WR
SRAM
to
Figure 30-12 on page 383
Table 30-9 on
38. It is impor-
30
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