ATMEGA256RZAV-8MU Atmel, ATMEGA256RZAV-8MU Datasheet - Page 163
ATMEGA256RZAV-8MU
Manufacturer Part Number
ATMEGA256RZAV-8MU
Description
MCU ATMEGA2561/AT86RF230 64-QFN
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA640V-8CU.pdf
(38 pages)
2.ATMEGA640V-8CU.pdf
(444 pages)
3.AT86RF230-ZU.pdf
(98 pages)
Specifications of ATMEGA256RZAV-8MU
Frequency
2.4GHz
Modulation Or Protocol
802.15.4 Zigbee
Applications
ISM, ZigBee™
Power - Output
3dBm
Sensitivity
-101dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
15.5mA
Current - Transmitting
16.5mA
Data Interface
PCB, Surface Mount
Memory Size
256kB Flash, 4kB EEPROM, 8kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
64-QFN
Wireless Frequency
2.4 GHz
Interface Type
JTAG, SPI
Output Power
3 dBm
For Use With
ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Data Rate - Maximum
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
ATmega256
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA256RZAV-8MU
Manufacturer:
Atmel
Quantity:
135
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16.11.15 TCNT4H and TCNT4L –Timer/Counter 4
16.11.16 TCNT5H and TCNT5L –Timer/Counter 5
16.11.17 OCR1AH and OCR1AL – Output Compare Register 1 A
16.11.18 OCR1BH and OCR1BL – Output Compare Register 1 B
16.11.19 OCR1CH and OCR1CL – Output Compare Register 1 C
2549M–AVR–09/10
The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers.
Registers” on page 138.
Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a com-
pare match between TCNTn and one of the OCRnx Registers.
Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock
for all compare units.
Bit
(0xA5)
(0xA4)
Read/Write
Initial Value
Bit
(0x125)
(0x124)
Read/Write
Initial Value
Bit
(0x89)
(0x88)
Read/Write
Initial Value
Bit
(0x8B)
(0x8A)
Read/Write
Initial Value
Bit
(0x8D)
(0x8C)
Read/Write
Initial Value
R/W
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
7
0
R/W
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
6
0
ATmega640/1280/1281/2560/2561
R/W
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
5
0
R/W
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
4
0
OCR1A[15:8]
OCR1B[15:8]
OCR1C[15:8]
TCNT4[15:8]
TCNT5[15:8]
OCR1A[7:0]
OCR1B[7:0]
OCR1C[7:0]
TCNT4[7:0]
TCNT5[7:0]
R/W
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
3
0
R/W
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
2
0
R/W
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
1
0
See “Accessing 16-bit
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
OCR1AH
OCR1BH
OCR1CH
OCR1AL
OCR1BL
OCR1CL
TCNT4H
TCNT4L
TCNT5H
TCNT5L
163
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