ATMEGA256RZAV-8AU Atmel, ATMEGA256RZAV-8AU Datasheet - Page 71
![MCU ATMEGA2561/AT86RF230 64-TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA256RZAV-8AU
Manufacturer Part Number
ATMEGA256RZAV-8AU
Description
MCU ATMEGA2561/AT86RF230 64-TQFP
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA640V-8CU.pdf
(38 pages)
2.ATMEGA640V-8CU.pdf
(444 pages)
3.AT86RF230-ZU.pdf
(98 pages)
Specifications of ATMEGA256RZAV-8AU
Frequency
2.4GHz
Modulation Or Protocol
802.15.4 Zigbee
Applications
ISM, ZigBee™
Power - Output
3dBm
Sensitivity
-101dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
15.5mA
Current - Transmitting
16.5mA
Data Interface
PCB, Surface Mount
Memory Size
256kB Flash, 4kB EEPROM, 8kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
64-TQFP
Wireless Frequency
2.4 GHz
Interface Type
JTAG, SPI
Output Power
3 dBm
For Use With
ATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Data Rate - Maximum
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
ATmega256
- Current page: 71 of 444
- Download datasheet (10Mb)
12.2
12.2.1
2549M–AVR–09/10
Ports as General Digital I/O
Configuring the Pin
Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the port as general digital I/O.
The ports are bi-directional I/O ports with optional internal pull-ups.
tional description of one I/O-port pin, here generically called Pxn.
Figure 12-2. General Digital I/O
Note:
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in
34 and Table 12-35 relates the alternate functions of Port L to the overriding signals shown in
Figure 12-5 on page 76.” on page
PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to
be configured as an output pin. The port pins are tri-stated when reset condition becomes active,
even if no clocks are running.
Pxn
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
SLEEP, and PUD are common to all ports.
PUD:
SLEEP:
clk
I/O
:
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
ATmega640/1280/1281/2560/2561
SLEEP
(1)
99, the DDxn bits are accessed at the DDRx I/O address, the
SYNCHRONIZER
D
L
Q
Q
D
PINxn
Q
Q
RESET
RESET
PORTxn
WDx:
RDx:
WRx:
RRx:
RPx:
WPx:
Q
Q
Q
Q
DDxn
CLR
CLR
D
D
RRx
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx REGISTER
PUD
WDx
RDx
RPx
clk
1
0
Figure 12-2
I/O
WRx
WPx
shows a func-
“Table 12-
71
I/O
,
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