ATMEGA256RZAV-8AU Atmel, ATMEGA256RZAV-8AU Datasheet - Page 295
ATMEGA256RZAV-8AU
Manufacturer Part Number
ATMEGA256RZAV-8AU
Description
MCU ATMEGA2561/AT86RF230 64-TQFP
Manufacturer
Atmel
Series
ATMEGAr
Datasheets
1.ATMEGA640V-8CU.pdf
(38 pages)
2.ATMEGA640V-8CU.pdf
(444 pages)
3.AT86RF230-ZU.pdf
(98 pages)
Specifications of ATMEGA256RZAV-8AU
Frequency
2.4GHz
Modulation Or Protocol
802.15.4 Zigbee
Applications
ISM, ZigBee™
Power - Output
3dBm
Sensitivity
-101dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
15.5mA
Current - Transmitting
16.5mA
Data Interface
PCB, Surface Mount
Memory Size
256kB Flash, 4kB EEPROM, 8kB RAM
Antenna Connector
PCB, Surface Mount
Package / Case
64-TQFP
Wireless Frequency
2.4 GHz
Interface Type
JTAG, SPI
Output Power
3 dBm
For Use With
ATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Data Rate - Maximum
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
ATmega256
- Current page: 295 of 444
- Download datasheet (10Mb)
25.8.6
25.8.7
2549M–AVR–09/10
DIDR0 – Digital Input Disable Register 0
DIDR2 – Digital Input Disable Register 2
ger source that is cleared to a trigger source that is set, will generate a positive edge on the
trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running
mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set
Table 25-6.
Note:
• Bit 7:0 – ADC7D:ADC0D: ADC7:0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an
analog signal is applied to the ADC7:0 pin and the digital input from this pin is not needed, this
bit should be written logic one to reduce power consumption in the digital input buffer.
• Bit 7:0 – ADC15D:ADC8D: ADC15:8 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an
analog signal is applied to the ADC15:8 pin and the digital input from this pin is not needed, this
bit should be written logic one to reduce power consumption in the digital input buffer.
Bit
(0x7E)
Read/Write
Initial Value
Bit
(0x7D)
Read/Write
Initial Value
ADTS2
Free running mode cannot be used for differential channels (see chapter
on page
0
0
0
0
1
1
1
1
ADC15D
ADC7D
ADC Auto Trigger Source Selections
R/W
R/W
7
0
7
0
281).
ADC14D
ADC6D
R/W
R/W
ADTS1
6
0
6
0
0
0
1
1
0
0
1
1
ADC13D
ATmega640/1280/1281/2560/2561
ADC5D
R/W
R/W
5
0
5
0
ADC12D
ADC4D
R/W
R/W
ADTS0
4
0
4
0
0
1
0
1
0
1
0
1
ADC11D
ADC3D
R/W
R/W
3
0
3
0
Trigger Source
Free Running mode
Analog Comparator
External Interrupt Request 0
Timer/Counter0 Compare Match A
Timer/Counter0 Overflow
Timer/Counter1 Compare Match B
Timer/Counter1 Overflow
Timer/Counter1 Capture Event
ADC10D
ADC2D
R/W
R/W
2
0
2
0
ADC1D
ADC9D
R/W
R/W
1
0
1
0
“Differential Channels”
ADC0D
ADC8D
R/W
R/W
0
0
0
0
.
DIDR0
DIDR2
295
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